#define SI_NUM_CONST_BUFFERS 16
#define SI_NUM_IMAGES 16
#define SI_NUM_IMAGE_SLOTS (SI_NUM_IMAGES * 2) /* the second half are FMASK slots */
-#define SI_NUM_SHADER_BUFFERS 16
+#define SI_NUM_SHADER_BUFFERS 32
struct si_screen;
struct si_shader;
enum radeon_bo_priority priority_constbuf : 6;
/* The i-th bit is set if that element is enabled (non-NULL resource). */
- unsigned enabled_mask;
- unsigned writable_mask;
+ uint64_t enabled_mask;
+ uint64_t writable_mask;
};
#define si_pm4_state_changed(sctx, member) \
struct util_queue_fence *ready_fence,
struct si_compiler_ctx_state *compiler_ctx_state, void *job,
util_queue_execute_func execute);
-void si_get_active_slot_masks(const struct si_shader_info *info, uint32_t *const_and_shader_buffers,
+void si_get_active_slot_masks(const struct si_shader_info *info, uint64_t *const_and_shader_buffers,
uint64_t *samplers_and_images);
int si_shader_select_with_key(struct si_screen *sscreen, struct si_shader_ctx_state *state,
struct si_compiler_ctx_state *compiler_state,
static inline unsigned si_get_constbuf_slot(unsigned slot)
{
- /* Constant buffers are in slots [16..31], ascending */
+ /* Constant buffers are in slots [32..47], ascending */
return SI_NUM_SHADER_BUFFERS + slot;
}
static inline unsigned si_get_shaderbuf_slot(unsigned slot)
{
- /* shader buffers are in slots [15..0], descending */
+ /* shader buffers are in slots [31..0], descending */
return SI_NUM_SHADER_BUFFERS - 1 - slot;
}