radeonsi: change PIPE_SHADER to MESA_SHADER (si_shader_context::type)

[mesa.git] / src / gallium / drivers / radeonsi / si_state.h

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 6cb8814602699a20026364452a6764c14dae920b..bb7a73c938e58bb8a9eb2dc2956fb16717470827 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -37,7 +37,7 @@
 #define SI_NUM_CONST_BUFFERS  16
 #define SI_NUM_IMAGES         16
 #define SI_NUM_IMAGE_SLOTS    (SI_NUM_IMAGES * 2) /* the second half are FMASK slots */
-#define SI_NUM_SHADER_BUFFERS 16
+#define SI_NUM_SHADER_BUFFERS 32
 
 struct si_screen;
 struct si_shader;
@@ -176,7 +176,7 @@ struct si_vertex_elements {
 };
 
 union si_state {
-   struct {
+   struct si_state_named {
       struct si_state_blend *blend;
       struct si_state_rasterizer *rasterizer;
       struct si_state_dsa *dsa;
@@ -189,7 +189,7 @@ union si_state {
       struct si_pm4_state *vs;
       struct si_pm4_state *ps;
    } named;
-   struct si_pm4_state *array[0];
+   struct si_pm4_state *array[sizeof(struct si_state_named) / sizeof(struct si_pm4_state *)];
 };
 
 #define SI_STATE_IDX(name) (offsetof(union si_state, named.name) / sizeof(struct si_pm4_state *))
@@ -203,7 +203,7 @@ static inline unsigned si_states_that_always_roll_context(void)
 }
 
 union si_state_atoms {
-   struct {
+   struct si_atoms_s {
       /* The order matters. */
       struct si_atom render_cond;
       struct si_atom streamout_begin;
@@ -228,11 +228,11 @@ union si_state_atoms {
       struct si_atom window_rectangles;
       struct si_atom shader_query;
    } s;
-   struct si_atom array[0];
+   struct si_atom array[sizeof(struct si_atoms_s) / sizeof(struct si_atom)];
 };
 
 #define SI_ATOM_BIT(name) (1 << (offsetof(union si_state_atoms, s.name) / sizeof(struct si_atom)))
-#define SI_NUM_ATOMS      (sizeof(union si_state_atoms) / sizeof(struct si_atom *))
+#define SI_NUM_ATOMS      (sizeof(union si_state_atoms) / sizeof(struct si_atom))
 
 static inline unsigned si_atoms_that_always_roll_context(void)
 {
@@ -457,8 +457,8 @@ struct si_buffer_resources {
    enum radeon_bo_priority priority_constbuf : 6;
 
    /* The i-th bit is set if that element is enabled (non-NULL resource). */
-   unsigned enabled_mask;
-   unsigned writable_mask;
+   uint64_t enabled_mask;
+   uint64_t writable_mask;
 };
 
 #define si_pm4_state_changed(sctx, member)                                                         \
@@ -501,7 +501,10 @@ bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 void si_release_all_descriptors(struct si_context *sctx);
 void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx);
 void si_compute_resources_add_all_to_bo_list(struct si_context *sctx);
-void si_all_descriptors_begin_new_cs(struct si_context *sctx);
+bool si_gfx_resources_check_encrypted(struct si_context *sctx);
+bool si_compute_resources_check_encrypted(struct si_context *sctx);
+void si_shader_pointers_mark_dirty(struct si_context *sctx);
+void si_add_all_descriptors_to_bo_list(struct si_context *sctx);
 void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf, const uint8_t *ptr,
                             unsigned size, uint32_t *const_offset);
 void si_update_all_texture_descriptors(struct si_context *sctx);
@@ -524,6 +527,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf);
 void si_init_state_compute_functions(struct si_context *sctx);
 void si_init_state_functions(struct si_context *sctx);
 void si_init_screen_state_functions(struct si_screen *sscreen);
+void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing);
 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
                                enum pipe_format format, unsigned offset, unsigned size,
                                uint32_t *state);
@@ -563,11 +567,11 @@ void si_init_screen_live_shader_cache(struct si_screen *sscreen);
 void si_init_shader_functions(struct si_context *sctx);
 bool si_init_shader_cache(struct si_screen *sscreen);
 void si_destroy_shader_cache(struct si_screen *sscreen);
-void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
+void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage,
                                  struct util_queue_fence *ready_fence,
                                  struct si_compiler_ctx_state *compiler_ctx_state, void *job,
                                  util_queue_execute_func execute);
-void si_get_active_slot_masks(const struct si_shader_info *info, uint32_t *const_and_shader_buffers,
+void si_get_active_slot_masks(const struct si_shader_info *info, uint64_t *const_and_shader_buffers,
                               uint64_t *samplers_and_images);
 int si_shader_select_with_key(struct si_screen *sscreen, struct si_shader_ctx_state *state,
                               struct si_compiler_ctx_state *compiler_state,
@@ -598,13 +602,13 @@ void si_init_streamout_functions(struct si_context *sctx);
 
 static inline unsigned si_get_constbuf_slot(unsigned slot)
 {
-   /* Constant buffers are in slots [16..31], ascending */
+   /* Constant buffers are in slots [32..47], ascending */
    return SI_NUM_SHADER_BUFFERS + slot;
 }
 
 static inline unsigned si_get_shaderbuf_slot(unsigned slot)
 {
-   /* shader buffers are in slots [15..0], descending */
+   /* shader buffers are in slots [31..0], descending */
    return SI_NUM_SHADER_BUFFERS - 1 - slot;
 }