radeonsi: limit DPBB context_states_per_bin batches when using gfx9 workaround

[mesa.git] / src / gallium / drivers / radeonsi / si_state_binning.c

diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index ba599e055e209c6f283167e71741bc2f6ec8d6bd..a361ea253c32e20e332455c4fa2da5701befeaf7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -563,8 +563,13 @@ void si_emit_dpbb_state(struct si_context *sctx)
                context_states_per_bin = 1;
                persistent_states_per_bin = 1;
        } else {
-               context_states_per_bin = 6;
-               persistent_states_per_bin = 32;
+               /* This is a workaround for:
+                *    https://bugs.freedesktop.org/show_bug.cgi?id=110214
+                * (an alternative is to insert manual BATCH_BREAK event when
+                * a context_roll is detected). */
+               context_states_per_bin = sctx->screen->has_gfx9_scissor_bug ? 1 : 6;
+               /* Using 32 here can cause GPU hangs on RAVEN1 */
+               persistent_states_per_bin = 16;
        }
        fpovs_per_batch = 63;
 
@@ -589,7 +594,10 @@ void si_emit_dpbb_state(struct si_context *sctx)
                S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
                S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
                S_028C44_OPTIMAL_BIN_SELECTION(1) |
-               G_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->last_binning_enabled != 1));
+               S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx->family == CHIP_VEGA12 ||
+                                                     sctx->family == CHIP_VEGA20 ||
+                                                     sctx->family >= CHIP_RAVEN2) &&
+                                                    sctx->last_binning_enabled != 1));
 
        unsigned db_dfsm_control = sctx->chip_class >= GFX10 ? R_028038_DB_DFSM_CONTROL
                                                             : R_028060_DB_DFSM_CONTROL;