radeonsi: move nir_shader_compiler_options into si_screen

[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index c7223d9412204fc28c2d32a404fcee336641eafc..c7a3f992a212172490bd02fd32ec0be80c4848d7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -527,22 +527,22 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
 static unsigned si_conv_prim_to_gs_out(unsigned mode)
 {
    static const int prim_conv[] = {
-      [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
-      [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
-      [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
-      [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
-      [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-      [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-      [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-      [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-      [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-      [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-      [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
-      [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
-      [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-      [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-      [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
-      [SI_PRIM_RECTANGLE_LIST] = V_028A6C_VGT_OUT_RECT_V0,
+      [PIPE_PRIM_POINTS] = V_028A6C_POINTLIST,
+      [PIPE_PRIM_LINES] = V_028A6C_LINESTRIP,
+      [PIPE_PRIM_LINE_LOOP] = V_028A6C_LINESTRIP,
+      [PIPE_PRIM_LINE_STRIP] = V_028A6C_LINESTRIP,
+      [PIPE_PRIM_TRIANGLES] = V_028A6C_TRISTRIP,
+      [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_TRISTRIP,
+      [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_TRISTRIP,
+      [PIPE_PRIM_QUADS] = V_028A6C_TRISTRIP,
+      [PIPE_PRIM_QUAD_STRIP] = V_028A6C_TRISTRIP,
+      [PIPE_PRIM_POLYGON] = V_028A6C_TRISTRIP,
+      [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_LINESTRIP,
+      [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_LINESTRIP,
+      [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_TRISTRIP,
+      [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_TRISTRIP,
+      [PIPE_PRIM_PATCHES] = V_028A6C_POINTLIST,
+      [SI_PRIM_RECTANGLE_LIST] = V_028A6C_RECTLIST,
    };
    assert(mode < ARRAY_SIZE(prim_conv));
 
@@ -761,7 +761,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
 
    /* draw packet */
    if (index_size) {
-      if (index_size != sctx->last_index_size) {
+      /* Register shadowing doesn't shadow INDEX_TYPE. */
+      if (index_size != sctx->last_index_size || sctx->shadowed_regs) {
          unsigned index_type;
 
          /* index type */
@@ -880,7 +881,9 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
    } else {
       int base_vertex;
 
-      if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
+      /* Register shadowing requires that we always emit PKT3_NUM_INSTANCES. */
+      if (sctx->shadowed_regs ||
+          sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
           sctx->last_instance_count != instance_count) {
          radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
          radeon_emit(cs, instance_count);
@@ -1864,7 +1867,8 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
    /* Update NGG culling settings. */
    if (sctx->ngg && !dispatch_prim_discard_cs && rast_prim == PIPE_PRIM_TRIANGLES &&
        !sctx->gs_shader.cso && /* GS doesn't support NGG culling. */
-       (sctx->screen->always_use_ngg_culling ||
+       (sctx->screen->always_use_ngg_culling_all ||
+        (sctx->tes_shader.cso && sctx->screen->always_use_ngg_culling_tess) ||
         /* At least 1024 non-indexed vertices (8 subgroups) are needed
          * per draw call (no TES/GS) to enable NGG culling.
          */