radeonsi: merge uses_persp_opcode_interp_sample/uses_linear_opcode_interp_sample

[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 11fc10a92e3689abfa6a0ba4210ceb8034fa1c42..400b0de6cc6e9ffb08796bc8eb54c22bb4960434 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1750,8 +1750,8 @@ static void si_shader_selector_key_hw_vs(struct si_context *sctx, struct si_shad
    struct si_shader_selector *ps = sctx->ps_shader.cso;
 
    key->opt.clip_disable = sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
-                           (vs->info.clipdist_writemask || vs->info.writes_clipvertex) &&
-                           !vs->info.culldist_writemask;
+                           (vs->info.base.clip_distance_array_size || vs->info.writes_clipvertex) &&
+                           !vs->info.base.cull_distance_array_size;
 
    /* Find out if PS is disabled. */
    bool ps_disabled = true;
@@ -1889,7 +1889,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_sh
       struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
       struct si_state_blend *blend = sctx->queued.named.blend;
 
-      if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
+      if (sel->info.color0_writes_all_cbufs &&
           sel->info.colors_written == 0x1)
          key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
 
@@ -1980,8 +1980,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_sh
                                                              sel->info.uses_linear_sample >
                                                           1;
 
-         if (sel->info.uses_persp_opcode_interp_sample ||
-             sel->info.uses_linear_opcode_interp_sample)
+         if (sel->info.uses_interp_at_sample)
             key->mono.u.ps.interpolate_at_sample_force_center = 1;
       }
 
@@ -2543,12 +2542,12 @@ void si_get_active_slot_masks(const struct si_shader_info *info, uint64_t *const
 {
    unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
 
-   num_shaderbufs = util_last_bit(info->shader_buffers_declared);
-   num_constbufs = util_last_bit(info->const_buffers_declared);
+   num_shaderbufs = info->base.num_ssbos;
+   num_constbufs = info->base.num_ubos;
    /* two 8-byte images share one 16-byte slot */
-   num_images = align(util_last_bit(info->images_declared), 2);
-   num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
-   num_samplers = util_last_bit(info->samplers_declared);
+   num_images = align(info->base.num_images, 2);
+   num_msaa_images = align(util_last_bit(info->base.msaa_images), 2);
+   num_samplers = util_last_bit(info->base.textures_used);
 
    /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
    start = si_get_shaderbuf_slot(num_shaderbufs - 1);
@@ -2755,8 +2754,10 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
    if (sctx->chip_class <= GFX9)
       sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
 
-   sel->clipdist_mask = sel->info.writes_clipvertex ? SIX_BITS : sel->info.clipdist_writemask;
-   sel->culldist_mask = sel->info.culldist_writemask << sel->info.num_written_clipdistance;
+   sel->clipdist_mask = sel->info.writes_clipvertex ? SIX_BITS :
+                           u_bit_consecutive(0, sel->info.base.clip_distance_array_size);
+   sel->culldist_mask = u_bit_consecutive(0, sel->info.base.cull_distance_array_size) <<
+                        sel->info.base.clip_distance_array_size;
 
    /* DB_SHADER_CONTROL */
    sel->db_shader_control = S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |