s/Tungsten Graphics/VMware/

[mesa.git] / src / gallium / drivers / softpipe / sp_tex_tile_cache.h

diff --git a/src/gallium/drivers/softpipe/sp_tex_tile_cache.h b/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
index 2220955b715cb12a39151ac00ef8aa708f3e84a3..4eb42460552667899e155524b93ae3650630f353 100644 (file)
--- a/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
+++ b/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
@@ -1,6 +1,6 @@
 /**************************************************************************
  * 
- * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2007 VMware, Inc.
  * All Rights Reserved.
  * 
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -18,7 +18,7 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -40,11 +40,11 @@ struct softpipe_tex_tile_cache;
 /**
  * Cache tile size (width and height). This needs to be a power of two.
  */
-#define TILE_SIZE_LOG2 6
-#define TILE_SIZE (1 << TILE_SIZE_LOG2)
+#define TEX_TILE_SIZE_LOG2 5
+#define TEX_TILE_SIZE (1 << TEX_TILE_SIZE_LOG2)
 
 
-#define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TILE_SIZE_LOG2)
+#define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TEX_TILE_SIZE_LOG2)
 #define TEX_Z_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1)
 
 /**
@@ -67,11 +67,19 @@ struct softpipe_tex_cached_tile
 {
    union tex_tile_address addr;
    union {
-      float color[TILE_SIZE][TILE_SIZE][4];
+      float color[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
+      unsigned int colorui[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
+      int colori[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
    } data;
 };
 
-#define NUM_ENTRIES 50
+/*
+ * The number of cache entries.
+ * Should not be decreased to lower than 16, and even that
+ * seems too low to avoid cache thrashing in some cases (because
+ * the cache is direct mapped, see tex_cache_pos() function).
+ */
+#define NUM_TEX_TILE_ENTRIES 16
 
 struct softpipe_tex_tile_cache
 {
@@ -82,7 +90,7 @@ struct softpipe_tex_tile_cache
    struct pipe_resource *texture;  /**< if caching a texture */
    unsigned timestamp;
 
-   struct softpipe_tex_cached_tile entries[NUM_ENTRIES];
+   struct softpipe_tex_cached_tile entries[NUM_TEX_TILE_ENTRIES];
 
    struct pipe_transfer *tex_trans;
    void *tex_trans_map;
@@ -92,7 +100,7 @@ struct softpipe_tex_tile_cache
    unsigned swizzle_g;
    unsigned swizzle_b;
    unsigned swizzle_a;
-   unsigned format;
+   enum pipe_format format;
 
    struct softpipe_tex_cached_tile *last_tile;  /**< most recently retrieved tile */
 };
@@ -104,13 +112,6 @@ sp_create_tex_tile_cache( struct pipe_context *pipe );
 extern void
 sp_destroy_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
 
-
-extern void
-sp_tex_tile_cache_map_transfers(struct softpipe_tex_tile_cache *tc);
-
-extern void
-sp_tex_tile_cache_unmap_transfers(struct softpipe_tex_tile_cache *tc);
-
 extern void
 sp_tex_tile_cache_set_sampler_view(struct softpipe_tex_tile_cache *tc,
                                    struct pipe_sampler_view *view);
@@ -125,7 +126,7 @@ sp_flush_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
 
 extern const struct softpipe_tex_cached_tile *
 sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc, 
-                         union tex_tile_address addr );
+                        union tex_tile_address addr );
 
 static INLINE union tex_tile_address
 tex_tile_address( unsigned x,
@@ -137,8 +138,8 @@ tex_tile_address( unsigned x,
    union tex_tile_address addr;
 
    addr.value = 0;
-   addr.bits.x = x / TILE_SIZE;
-   addr.bits.y = y / TILE_SIZE;
+   addr.bits.x = x / TEX_TILE_SIZE;
+   addr.bits.y = y / TEX_TILE_SIZE;
    addr.bits.z = z;
    addr.bits.face = face;
    addr.bits.level = level;
@@ -150,7 +151,7 @@ tex_tile_address( unsigned x,
  */
 static INLINE const struct softpipe_tex_cached_tile *
 sp_get_cached_tile_tex(struct softpipe_tex_tile_cache *tc, 
-                         union tex_tile_address addr )
+                       union tex_tile_address addr )
 {
    if (tc->last_tile->addr.value == addr.value)
       return tc->last_tile;