Gallium: Add format PIPE_FORMAT_R8_SRGB

[mesa.git] / src / gallium / drivers / svga / svga_state_rss.c

diff --git a/src/gallium/drivers/svga/svga_state_rss.c b/src/gallium/drivers/svga/svga_state_rss.c
index 515155d3ae8cf410ac6330f212935bf15eaa26d1..786839f705189f0a056391142d256294f1c86e35 100644 (file)
--- a/src/gallium/drivers/svga/svga_state_rss.c
+++ b/src/gallium/drivers/svga/svga_state_rss.c
@@ -75,6 +75,23 @@ svga_queue_rs(struct rs_queue *q, unsigned rss, unsigned value)
 }
 
 
+static unsigned
+translate_fill_mode(unsigned fill)
+{
+   switch (fill) {
+   case PIPE_POLYGON_MODE_POINT:
+      return SVGA3D_FILLMODE_POINT;
+   case PIPE_POLYGON_MODE_LINE:
+      return SVGA3D_FILLMODE_LINE;
+   case PIPE_POLYGON_MODE_FILL:
+      return SVGA3D_FILLMODE_FILL;
+   default:
+      assert(!"Bad fill mode");
+      return SVGA3D_FILLMODE_FILL;
+   }
+}
+
+
 /* Compare old and new render states and emit differences between them
  * to hardware.  Simplest implementation would be to emit the whole of
  * the "to" state.
@@ -207,6 +224,8 @@ emit_rss_vgpu9(struct svga_context *svga, unsigned dirty)
        */
       EMIT_RS(svga, curr->shademode, SHADEMODE);
 
+      EMIT_RS(svga, translate_fill_mode(curr->hw_fillmode), FILLMODE);
+
       /* Don't do culling while the software pipeline is active.  It
        * does it for us, and additionally introduces potentially
        * back-facing triangles.
@@ -275,29 +294,24 @@ emit_rss_vgpu9(struct svga_context *svga, unsigned dirty)
    if (queue.rs_count) {
       SVGA3dRenderState *rs;
 
-      if (SVGA3D_BeginSetRenderState(svga->swc,
-                                      &rs,
-                                      queue.rs_count) != PIPE_OK)
-         goto fail;
+      if (SVGA3D_BeginSetRenderState(svga->swc, &rs, queue.rs_count)
+          != PIPE_OK) {
+         /* XXX: need to poison cached hardware state on failure to ensure
+          * dirty state gets re-emitted.  Fix this by re-instating partial
+          * FIFOCommit command and only updating cached hw state once the
+          * initial allocation has succeeded.
+          */
+         memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs));
+
+         return PIPE_ERROR_OUT_OF_MEMORY;
+      }
 
-      memcpy(rs,
-              queue.rs,
-              queue.rs_count * sizeof queue.rs[0]);
+      memcpy(rs, queue.rs, queue.rs_count * sizeof queue.rs[0]);
 
       SVGA_FIFOCommitAll(svga->swc);
    }
 
    return PIPE_OK;
-
-fail:
-   /* XXX: need to poison cached hardware state on failure to ensure
-    * dirty state gets re-emitted.  Fix this by re-instating partial
-    * FIFOCommit command and only updating cached hw state once the
-    * initial allocation has succeeded.
-    */
-   memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs));
-
-   return PIPE_ERROR_OUT_OF_MEMORY;
 }