radeonsi: fix user fence space when MCBP is enabled

[mesa.git] / src / gallium / drivers / v3d / v3dx_format_table.c

diff --git a/src/gallium/drivers/v3d/v3dx_format_table.c b/src/gallium/drivers/v3d/v3dx_format_table.c
index 100fd3b0da48d1c868a39332be5d41a3dd03dd43..0d51ff44c0a6cd8ef65e911f7183b912c6dc8e7b 100644 (file)
--- a/src/gallium/drivers/v3d/v3dx_format_table.c
+++ b/src/gallium/drivers/v3d/v3dx_format_table.c
@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-#include "util/u_format.h"
+#include "util/format/u_format.h"
 
 #include "v3d_context.h"
 #include "broadcom/cle/v3dx_pack.h"
@@ -147,12 +147,13 @@ static const struct v3d_format format_table[] = {
 #if V3D_VERSION >= 40
         FORMAT(S8_UINT_Z24_UNORM, D24S8,        DEPTH24_X8,  SWIZ_XXXX, 32, 1),
         FORMAT(X8Z24_UNORM,       D24S8,        DEPTH24_X8,  SWIZ_XXXX, 32, 1),
-        FORMAT(S8X24_UINT,        S8,           DEPTH_COMP32F, SWIZ_XXXX, 32, 1),
+        FORMAT(S8X24_UINT,        S8,           RGBA8UI, SWIZ_XXXX, 16, 1),
         FORMAT(Z32_FLOAT,         D32F,         DEPTH_COMP32F, SWIZ_XXXX, 32, 1),
         FORMAT(Z16_UNORM,         D16,          DEPTH_COMP16,SWIZ_XXXX, 32, 1),
 
         /* Pretend we support this, but it'll be separate Z32F depth and S8. */
         FORMAT(Z32_FLOAT_S8X24_UINT, D32F,      DEPTH_COMP32F, SWIZ_XXXX, 32, 1),
+        FORMAT(X32_S8X24_UINT,    S8,           R8UI,          SWIZ_XXXX, 16, 1),
 #else
         FORMAT(S8_UINT_Z24_UNORM, ZS_DEPTH24_STENCIL8, DEPTH24_X8, SWIZ_XXXX, 32, 1),
         FORMAT(X8Z24_UNORM,       ZS_DEPTH24_STENCIL8, DEPTH24_X8, SWIZ_XXXX, 32, 1),
@@ -176,8 +177,13 @@ static const struct v3d_format format_table[] = {
         FORMAT(ETC2_RG11_SNORM,   NO,           SIGNED_RG11_EAC, SWIZ_XY01, 16, 0),
 
         FORMAT(DXT1_RGB,          NO,           BC1,         SWIZ_XYZ1, 16, 0),
-        FORMAT(DXT3_RGBA,         NO,           BC2,         SWIZ_XYZ1, 16, 0),
-        FORMAT(DXT5_RGBA,         NO,           BC3,         SWIZ_XYZ1, 16, 0),
+        FORMAT(DXT1_SRGB,         NO,           BC1,         SWIZ_XYZ1, 16, 0),
+        FORMAT(DXT1_RGBA,         NO,           BC1,         SWIZ_XYZW, 16, 0),
+        FORMAT(DXT1_SRGBA,        NO,           BC1,         SWIZ_XYZW, 16, 0),
+        FORMAT(DXT3_RGBA,         NO,           BC2,         SWIZ_XYZW, 16, 0),
+        FORMAT(DXT3_SRGBA,        NO,           BC2,         SWIZ_XYZW, 16, 0),
+        FORMAT(DXT5_RGBA,         NO,           BC3,         SWIZ_XYZW, 16, 0),
+        FORMAT(DXT5_SRGBA,        NO,           BC3,         SWIZ_XYZW, 16, 0),
 };
 
 const struct v3d_format *
@@ -318,3 +324,34 @@ v3dX(get_internal_type_bpp_for_output_format)(uint32_t format,
                 break;
         }
 }
+
+bool
+v3dX(tfu_supports_tex_format)(enum V3DX(Texture_Data_Formats) format)
+{
+        switch (format) {
+        case TEXTURE_DATA_FORMAT_R8:
+        case TEXTURE_DATA_FORMAT_R8_SNORM:
+        case TEXTURE_DATA_FORMAT_RG8:
+        case TEXTURE_DATA_FORMAT_RG8_SNORM:
+        case TEXTURE_DATA_FORMAT_RGBA8:
+        case TEXTURE_DATA_FORMAT_RGBA8_SNORM:
+        case TEXTURE_DATA_FORMAT_RGB565:
+        case TEXTURE_DATA_FORMAT_RGBA4:
+        case TEXTURE_DATA_FORMAT_RGB5_A1:
+        case TEXTURE_DATA_FORMAT_RGB10_A2:
+        case TEXTURE_DATA_FORMAT_R16:
+        case TEXTURE_DATA_FORMAT_R16_SNORM:
+        case TEXTURE_DATA_FORMAT_RG16:
+        case TEXTURE_DATA_FORMAT_RG16_SNORM:
+        case TEXTURE_DATA_FORMAT_RGBA16:
+        case TEXTURE_DATA_FORMAT_RGBA16_SNORM:
+        case TEXTURE_DATA_FORMAT_R16F:
+        case TEXTURE_DATA_FORMAT_RG16F:
+        case TEXTURE_DATA_FORMAT_RGBA16F:
+        case TEXTURE_DATA_FORMAT_R11F_G11F_B10F:
+        case TEXTURE_DATA_FORMAT_R4:
+                return true;
+        default:
+                return false;
+        }
+}