s/Tungsten Graphics/VMware/

[mesa.git] / src / gallium / include / pipe / p_defines.h

diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
index 2d38ce1a8c4a8edfc9f0a14504730039a2eb5cc5..bea0c96b7ce1fb66464dc004559e3b8edc487fec 100644 (file)
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -1,6 +1,6 @@
 /**************************************************************************
  * 
- * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2007 VMware, Inc.
  * All Rights Reserved.
  * 
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -18,7 +18,7 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -188,11 +188,22 @@ enum pipe_texture_target {
 /**
  * Clear buffer bits
  */
+#define PIPE_CLEAR_DEPTH        (1 << 0)
+#define PIPE_CLEAR_STENCIL      (1 << 1)
+#define PIPE_CLEAR_COLOR0       (1 << 2)
+#define PIPE_CLEAR_COLOR1       (1 << 3)
+#define PIPE_CLEAR_COLOR2       (1 << 4)
+#define PIPE_CLEAR_COLOR3       (1 << 5)
+#define PIPE_CLEAR_COLOR4       (1 << 6)
+#define PIPE_CLEAR_COLOR5       (1 << 7)
+#define PIPE_CLEAR_COLOR6       (1 << 8)
+#define PIPE_CLEAR_COLOR7       (1 << 9)
+/** Combined flags */
 /** All color buffers currently bound */
-#define PIPE_CLEAR_COLOR        (1 << 0)
-#define PIPE_CLEAR_DEPTH        (1 << 1)
-#define PIPE_CLEAR_STENCIL      (1 << 2)
-/** Depth/stencil combined */
+#define PIPE_CLEAR_COLOR        (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \
+                                 PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \
+                                 PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \
+                                 PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7)
 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)
 
 /**
@@ -330,9 +341,13 @@ enum pipe_flush_flags {
  * The shared flag is quite underspecified, but certainly isn't a
  * binding flag - it seems more like a message to the winsys to create
  * a shareable allocation.
+ * 
+ * The third flag has been added to be able to force textures to be created
+ * in linear mode (no tiling).
  */
 #define PIPE_BIND_SCANOUT     (1 << 14) /*  */
 #define PIPE_BIND_SHARED      (1 << 15) /* get_texture_handle ??? */
+#define PIPE_BIND_LINEAR      (1 << 21)
 
 
 /* Flags for the driver about resource behaviour:
@@ -482,7 +497,6 @@ enum pipe_cap {
    PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS = 55,
    PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS = 56,
    PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME = 57,
-   PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS = 58, /* temporary */
    PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS = 59, /* temporary */
    PIPE_CAP_VERTEX_COLOR_UNCLAMPED = 60,
    PIPE_CAP_VERTEX_COLOR_CLAMPED = 61,
@@ -506,12 +520,26 @@ enum pipe_cap {
    PIPE_CAP_TGSI_TEXCOORD = 79,
    PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER = 80,
    PIPE_CAP_QUERY_PIPELINE_STATISTICS = 81,
-   PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK = 82
+   PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK = 82,
+   PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE = 83,
+   PIPE_CAP_MAX_VIEWPORTS = 84,
+   PIPE_CAP_ENDIANNESS = 85,
+   PIPE_CAP_MIXED_FRAMEBUFFER_SIZES = 86,
+   PIPE_CAP_TGSI_VS_LAYER = 87
 };
 
 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
 
+enum pipe_endian {
+   PIPE_ENDIAN_LITTLE = 0,
+   PIPE_ENDIAN_BIG = 1,
+#if defined(PIPE_ARCH_LITTLE_ENDIAN)
+   PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE
+#elif defined(PIPE_ARCH_BIG_ENDIAN)
+   PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG
+#endif
+};
 
 /**
  * Implementation limits which are queried through
@@ -555,7 +583,8 @@ enum pipe_shader_cap
    PIPE_SHADER_CAP_INTEGERS = 17,
    PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS = 18,
    PIPE_SHADER_CAP_PREFERRED_IR = 19,
-   PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED = 20
+   PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED = 20,
+   PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS = 21
 };
 
 /**