* E.g. the state tracker could have a simpler path which maps textures and
* does read/modify/write cycles on them directly, and a more complicated
* path which uses minimal read and write transfers.
+ *
+ * This flag supresses implicit "DISCARD" for buffer_subdata.
*/
PIPE_TRANSFER_MAP_DIRECTLY = (1 << 2),
* PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
* the resource.
*/
- PIPE_TRANSFER_COHERENT = (1 << 14)
+ PIPE_TRANSFER_COHERENT = (1 << 14),
+
+ /**
+ * This and higher bits are reserved for private use by drivers. Drivers
+ * should use this as (PIPE_TRANSFER_DRV_PRV << i).
+ */
+ PIPE_TRANSFER_DRV_PRV = (1 << 24)
};
/**
PIPE_FLUSH_END_OF_FRAME = (1 << 0),
PIPE_FLUSH_DEFERRED = (1 << 1),
PIPE_FLUSH_FENCE_FD = (1 << 2),
+ PIPE_FLUSH_ASYNC = (1 << 3),
+ PIPE_FLUSH_HINT_FINISH = (1 << 4),
+ PIPE_FLUSH_TOP_OF_PIPE = (1 << 5),
+ PIPE_FLUSH_BOTTOM_OF_PIPE = (1 << 6),
};
/**
*/
#define PIPE_CONTEXT_PREFER_THREADED (1 << 3)
+/**
+ * Create a high priority context.
+ */
+#define PIPE_CONTEXT_HIGH_PRIORITY (1 << 4)
+
+/**
+ * Create a low priority context.
+ */
+#define PIPE_CONTEXT_LOW_PRIORITY (1 << 5)
+
+/** Stop execution if the device is reset. */
+#define PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET (1 << 6)
/**
* Flags for pipe_context::memory_barrier.
#define PIPE_BARRIER_FRAMEBUFFER (1 << 9)
#define PIPE_BARRIER_STREAMOUT_BUFFER (1 << 10)
#define PIPE_BARRIER_GLOBAL_BUFFER (1 << 11)
-#define PIPE_BARRIER_ALL ((1 << 12) - 1)
+#define PIPE_BARRIER_UPDATE_BUFFER (1 << 12)
+#define PIPE_BARRIER_UPDATE_TEXTURE (1 << 13)
+#define PIPE_BARRIER_ALL ((1 << 14) - 1)
+
+#define PIPE_BARRIER_UPDATE \
+ (PIPE_BARRIER_UPDATE_BUFFER | PIPE_BARRIER_UPDATE_TEXTURE)
/**
* Flags for pipe_context::texture_barrier.
#define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1)
#define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2)
#define PIPE_RESOURCE_FLAG_SPARSE (1 << 3)
-#define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 16) /* driver/winsys private */
+#define PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE (1 << 4)
+#define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 8) /* driver/winsys private */
#define PIPE_RESOURCE_FLAG_ST_PRIV (1 << 24) /* state-tracker/winsys private */
/**
PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE,
PIPE_QUERY_GPU_FINISHED,
PIPE_QUERY_PIPELINE_STATISTICS,
+ PIPE_QUERY_PIPELINE_STATISTICS_SINGLE,
PIPE_QUERY_TYPES,
/* start of driver queries, see pipe_screen::get_driver_query_info */
PIPE_QUERY_DRIVER_SPECIFIC = 256,
};
+/**
+ * Index for PIPE_QUERY_PIPELINE_STATISTICS subqueries.
+ */
+enum pipe_statistics_query_index {
+ PIPE_STAT_QUERY_IA_VERTICES,
+ PIPE_STAT_QUERY_IA_PRIMITIVES,
+ PIPE_STAT_QUERY_VS_INVOCATIONS,
+ PIPE_STAT_QUERY_GS_INVOCATIONS,
+ PIPE_STAT_QUERY_GS_PRIMITIVES,
+ PIPE_STAT_QUERY_C_INVOCATIONS,
+ PIPE_STAT_QUERY_C_PRIMITIVES,
+ PIPE_STAT_QUERY_PS_INVOCATIONS,
+ PIPE_STAT_QUERY_HS_INVOCATIONS,
+ PIPE_STAT_QUERY_DS_INVOCATIONS,
+ PIPE_STAT_QUERY_CS_INVOCATIONS,
+};
+
/**
* Conditional rendering modes
*/
};
+/**
+ * Conservative rasterization modes.
+ */
+enum pipe_conservative_raster_mode
+{
+ PIPE_CONSERVATIVE_RASTER_OFF,
+
+ /**
+ * The post-snap mode means the conservative rasterization occurs after
+ * the conversion from floating-point to fixed-point coordinates
+ * on the subpixel grid.
+ */
+ PIPE_CONSERVATIVE_RASTER_POST_SNAP,
+
+ /**
+ * The pre-snap mode means the conservative rasterization occurs before
+ * the conversion from floating-point to fixed-point coordinates.
+ */
+ PIPE_CONSERVATIVE_RASTER_PRE_SNAP,
+};
+
+
/**
* resource_get_handle flags.
*/
/* Requires pipe_context::flush_resource before external use. */
-#define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH (1 << 0)
+#define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH (1 << 0)
/* Expected external use of the resource: */
-#define PIPE_HANDLE_USAGE_READ (1 << 1)
-#define PIPE_HANDLE_USAGE_WRITE (1 << 2)
-#define PIPE_HANDLE_USAGE_READ_WRITE (PIPE_HANDLE_USAGE_READ | \
- PIPE_HANDLE_USAGE_WRITE)
+#define PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE (1 << 1)
+#define PIPE_HANDLE_USAGE_SHADER_WRITE (1 << 2)
/**
* pipe_image_view access flags.
*/
enum pipe_cap
{
+ PIPE_CAP_GRAPHICS,
PIPE_CAP_NPOT_TEXTURES,
- PIPE_CAP_TWO_SIDED_STENCIL,
PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS,
PIPE_CAP_ANISOTROPIC_FILTER,
PIPE_CAP_POINT_SPRITE,
PIPE_CAP_QUERY_TIME_ELAPSED,
PIPE_CAP_TEXTURE_SHADOW_MAP,
PIPE_CAP_TEXTURE_SWIZZLE,
- PIPE_CAP_MAX_TEXTURE_2D_LEVELS,
+ PIPE_CAP_MAX_TEXTURE_2D_SIZE,
PIPE_CAP_MAX_TEXTURE_3D_LEVELS,
PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS,
PIPE_CAP_TEXTURE_MIRROR_CLAMP,
PIPE_CAP_BLEND_EQUATION_SEPARATE,
- PIPE_CAP_SM3,
PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS,
PIPE_CAP_PRIMITIVE_RESTART,
/** blend enables and write masks per rendertarget */
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
PIPE_CAP_DEPTH_CLIP_DISABLE,
+ PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE,
PIPE_CAP_SHADER_STENCIL_EXPORT,
PIPE_CAP_TGSI_INSTANCEID,
PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR,
PIPE_CAP_VERTEX_COLOR_UNCLAMPED,
PIPE_CAP_VERTEX_COLOR_CLAMPED,
PIPE_CAP_GLSL_FEATURE_LEVEL,
+ PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY,
+ PIPE_CAP_ESSL_FEATURE_LEVEL,
PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION,
PIPE_CAP_USER_VERTEX_BUFFERS,
PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY,
PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY,
PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY,
PIPE_CAP_COMPUTE,
- PIPE_CAP_USER_CONSTANT_BUFFERS,
PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT,
PIPE_CAP_START_INSTANCE,
PIPE_CAP_QUERY_TIMESTAMP,
PIPE_CAP_MULTI_DRAW_INDIRECT,
PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS,
PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL,
+ PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL,
PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL,
PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT,
PIPE_CAP_INVALIDATE_BUFFER,
PIPE_CAP_MAX_WINDOW_RECTANGLES,
PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED,
PIPE_CAP_VIEWPORT_SUBPIXEL_BITS,
+ PIPE_CAP_RASTERIZER_SUBPIXEL_BITS,
PIPE_CAP_MIXED_COLOR_DEPTH_BITS,
PIPE_CAP_TGSI_ARRAY_COMPONENTS,
PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS,
PIPE_CAP_TGSI_CAN_READ_OUTPUTS,
PIPE_CAP_NATIVE_FENCE_FD,
PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY,
- PIPE_CAP_TGSI_FS_FBFETCH,
+ PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS,
+ PIPE_CAP_FBFETCH,
PIPE_CAP_TGSI_MUL_ZERO_WINS,
PIPE_CAP_DOUBLES,
PIPE_CAP_INT64,
PIPE_CAP_QUERY_SO_OVERFLOW,
PIPE_CAP_MEMOBJ,
PIPE_CAP_LOAD_CONSTBUF,
+ PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS,
+ PIPE_CAP_TILE_RASTER_ORDER,
+ PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES,
+ PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS,
+ PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET,
+ PIPE_CAP_CONTEXT_PRIORITY_MASK,
+ PIPE_CAP_FENCE_SIGNAL,
+ PIPE_CAP_CONSTBUF0_FLAGS,
+ PIPE_CAP_PACKED_UNIFORMS,
+ PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES,
+ PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES,
+ PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES,
+ PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES,
+ PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS,
+ PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE,
+ PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE,
+ PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS,
+ PIPE_CAP_MAX_GS_INVOCATIONS,
+ PIPE_CAP_MAX_SHADER_BUFFER_SIZE,
+ PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE,
+ PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS,
+ PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS,
+ PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS,
+ PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET,
+ PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET,
+ PIPE_CAP_SURFACE_SAMPLE_COUNT,
+ PIPE_CAP_TGSI_ATOMFADD,
+ PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE,
+ PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND,
+ PIPE_CAP_DEST_SURFACE_SRGB_CONTROL,
+ PIPE_CAP_NIR_COMPACT_ARRAYS,
+ PIPE_CAP_MAX_VARYINGS,
+ PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK,
+ PIPE_CAP_COMPUTE_SHADER_DERIVATIVES,
+ PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS,
+ PIPE_CAP_IMAGE_LOAD_FORMATTED,
+ PIPE_CAP_THROTTLE,
+ PIPE_CAP_DMABUF,
+ PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA,
+ PIPE_CAP_FRAGMENT_SHADER_INTERLOCK,
+ PIPE_CAP_FBFETCH_COHERENT,
+ PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED,
+ PIPE_CAP_ATOMIC_FLOAT_MINMAX,
+ PIPE_CAP_TGSI_DIV,
+ PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD,
+ PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES,
+ PIPE_CAP_VERTEX_SHADER_SATURATE,
+ PIPE_CAP_TEXTURE_SHADOW_LOD,
+ PIPE_CAP_SHADER_SAMPLES_IDENTICAL,
+ PIPE_CAP_TGSI_ATOMINC_WRAP,
+ PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF,
+ PIPE_CAP_GL_SPIRV,
+ PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS,
+ PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION,
+ PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE,
};
+/**
+ * Possible bits for PIPE_CAP_CONTEXT_PRIORITY_MASK param, which should
+ * return a bitmask of the supported priorities. If the driver does not
+ * support prioritized contexts, it can return 0.
+ *
+ * Note that these match __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_*
+ */
+#define PIPE_CONTEXT_PRIORITY_LOW (1 << 0)
+#define PIPE_CONTEXT_PRIORITY_MEDIUM (1 << 1)
+#define PIPE_CONTEXT_PRIORITY_HIGH (1 << 2)
+
#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
PIPE_CAPF_MAX_POINT_WIDTH_AA,
PIPE_CAPF_MAX_TEXTURE_ANISOTROPY,
PIPE_CAPF_MAX_TEXTURE_LOD_BIAS,
- PIPE_CAPF_GUARD_BAND_LEFT,
- PIPE_CAPF_GUARD_BAND_TOP,
- PIPE_CAPF_GUARD_BAND_RIGHT,
- PIPE_CAPF_GUARD_BAND_BOTTOM
+ PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE,
+ PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE,
+ PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY,
};
/** Shader caps not specific to any single stage */
PIPE_SHADER_CAP_LOWER_IF_THRESHOLD,
PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS,
PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED,
+ PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS,
+ PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS,
};
/**
enum pipe_shader_ir
{
PIPE_SHADER_IR_TGSI = 0,
- PIPE_SHADER_IR_LLVM,
PIPE_SHADER_IR_NATIVE,
PIPE_SHADER_IR_NIR,
+ PIPE_SHADER_IR_NIR_SERIALIZED,
};
/**
PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
};
+/**
+ * Resource parameters. They can be queried using
+ * pipe_screen::get_resource_param.
+ */
+enum pipe_resource_param
+{
+ PIPE_RESOURCE_PARAM_NPLANES,
+ PIPE_RESOURCE_PARAM_STRIDE,
+ PIPE_RESOURCE_PARAM_OFFSET,
+ PIPE_RESOURCE_PARAM_MODIFIER,
+ PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED,
+ PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS,
+ PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD,
+};
+
+/**
+ * Types of parameters for pipe_context::set_context_param.
+ */
+enum pipe_context_param
+{
+ /* A hint for the driver that it should pin its execution threads to
+ * a group of cores sharing a specific L3 cache if the CPU has multiple
+ * L3 caches. This is needed for good multithreading performance on
+ * AMD Zen CPUs. "value" is the L3 cache index. Drivers that don't have
+ * any internal threads or don't run on affected CPUs can ignore this.
+ */
+ PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
+};
+
/**
* Composite query types
*/
struct pipe_query_data_timestamp_disjoint
{
uint64_t frequency;
- boolean disjoint;
+ bool disjoint;
};
/**
/* PIPE_QUERY_SO_OVERFLOW_PREDICATE */
/* PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE */
/* PIPE_QUERY_GPU_FINISHED */
- boolean b;
+ bool b;
/* PIPE_QUERY_OCCLUSION_COUNTER */
/* PIPE_QUERY_TIMESTAMP */
unsigned num_queries;
};
+enum pipe_fd_type
+{
+ PIPE_FD_TYPE_NATIVE_SYNC,
+ PIPE_FD_TYPE_SYNCOBJ,
+};
+
enum pipe_debug_type
{
PIPE_DEBUG_TYPE_OUT_OF_MEMORY = 1,
projects / mesa.git / blobdiff