TGSI_SEMANTIC_SUBGROUP_GT_MASK,
TGSI_SEMANTIC_SUBGROUP_LE_MASK,
TGSI_SEMANTIC_SUBGROUP_LT_MASK,
+ TGSI_SEMANTIC_CS_USER_DATA_AMD,
+ TGSI_SEMANTIC_VIEWPORT_MASK,
+ TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL, /**< from set_tess_state */
+ TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL, /**< from set_tess_state */
TGSI_SEMANTIC_COUNT, /**< number of semantic values */
};
TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
TGSI_PROPERTY_MUL_ZERO_WINS,
+ TGSI_PROPERTY_VS_BLIT_SGPRS_AMD,
+ TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD,
+ TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE,
+ TGSI_PROPERTY_FS_BLEND_EQUATION_ADVANCED,
TGSI_PROPERTY_COUNT,
};
TGSI_OPCODE_EX2 = 28,
TGSI_OPCODE_LG2 = 29,
TGSI_OPCODE_POW = 30,
- /* gap */
+ TGSI_OPCODE_DEMOTE = 31,
TGSI_OPCODE_U2I64 = 32,
TGSI_OPCODE_CLOCK = 33,
TGSI_OPCODE_I2I64 = 34,
- /* gap */
+ TGSI_OPCODE_READ_HELPER = 35,
TGSI_OPCODE_COS = 36,
TGSI_OPCODE_DDX = 37,
TGSI_OPCODE_DDY = 38,
TGSI_OPCODE_BGNSUB = 100,
TGSI_OPCODE_ENDLOOP = 101,
TGSI_OPCODE_ENDSUB = 102,
- /* gap */
+ TGSI_OPCODE_ATOMFADD = 103,
TGSI_OPCODE_TXQS = 104,
TGSI_OPCODE_RESQ = 105,
TGSI_OPCODE_READ_FIRST = 106,
TGSI_OPCODE_LOD = 249,
- TGSI_OPCODE_LAST = 250,
+ TGSI_OPCODE_ATOMINC_WRAP = 250,
+ TGSI_OPCODE_ATOMDEC_WRAP = 251,
+
+ TGSI_OPCODE_LAST = 252,
};
#define TGSI_MEMORY_COHERENT (1 << 0)
#define TGSI_MEMORY_RESTRICT (1 << 1)
#define TGSI_MEMORY_VOLATILE (1 << 2)
+/* The "stream" cache policy will minimize memory cache usage if other
+ * memory operations need the cache.
+ */
+#define TGSI_MEMORY_STREAM_CACHE_POLICY (1 << 3)
/**
* Specifies the type of memory access to do for the LOAD/STORE instruction.
*/
struct tgsi_instruction_memory
{
- unsigned Qualifier : 3; /* TGSI_MEMORY_ */
+ unsigned Qualifier : 4; /* TGSI_MEMORY_ */
unsigned Texture : 8; /* only for images: TGSI_TEXTURE_ */
unsigned Format : 10; /* only for images: PIPE_FORMAT_ */
- unsigned Padding : 11;
+ unsigned Padding : 10;
};
#define TGSI_MEMBAR_SHADER_BUFFER (1 << 0)