r600g: use backend mask for occlusion queries

[mesa.git] / src / gallium / winsys / r600 / drm / r600_drm.c

diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index 311324f4f7135c2c3c00cf9b239fdd134cbbb847..8aa8c3df52a93d191bb0f24acd6edb50144326e9 100644 (file)
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -50,6 +50,14 @@
 #define RADEON_INFO_NUM_BACKENDS 0xa
 #endif
 
+#ifndef RADEON_INFO_NUM_TILE_PIPES
+#define RADEON_INFO_NUM_TILE_PIPES 0xb
+#endif
+
+#ifndef RADEON_INFO_BACKEND_MAP
+#define RADEON_INFO_BACKEND_MAP 0xd
+#endif
+
 enum radeon_family r600_get_family(struct radeon *r600)
 {
        return r600->family;
@@ -75,6 +83,16 @@ unsigned r600_get_num_backends(struct radeon *radeon)
        return radeon->num_backends;
 }
 
+unsigned r600_get_num_tile_pipes(struct radeon *radeon)
+{
+       return radeon->num_tile_pipes;
+}
+
+unsigned r600_get_backend_map(struct radeon *radeon)
+{
+       return radeon->backend_map;
+}
+
 unsigned r600_get_minor_version(struct radeon *radeon)
 {
        return radeon->minor_version;
@@ -156,7 +174,20 @@ static int eg_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
                return -EINVAL;
        }
 
-       radeon->tiling_info.num_banks = (tiling_config & 0xf0) >> 4;
+       switch ((tiling_config & 0xf0) >> 4) {
+       case 0:
+               radeon->tiling_info.num_banks = 4;
+               break;
+       case 1:
+               radeon->tiling_info.num_banks = 8;
+               break;
+       case 2:
+               radeon->tiling_info.num_banks = 16;
+               break;
+       default:
+               return -EINVAL;
+
+       }
 
        switch ((tiling_config & 0xf00) >> 8) {
        case 0:
@@ -173,7 +204,7 @@ static int eg_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
 
 static int radeon_drm_get_tiling(struct radeon *radeon)
 {
-       struct drm_radeon_info info;
+       struct drm_radeon_info info = {};
        int r;
        uint32_t tiling_config = 0;
 
@@ -195,8 +226,8 @@ static int radeon_drm_get_tiling(struct radeon *radeon)
 
 static int radeon_get_clock_crystal_freq(struct radeon *radeon)
 {
-       struct drm_radeon_info info;
-       uint32_t clock_crystal_freq;
+       struct drm_radeon_info info = {};
+       uint32_t clock_crystal_freq = 0;
        int r;
 
        info.request = RADEON_INFO_CLOCK_CRYSTAL_FREQ;
@@ -213,8 +244,8 @@ static int radeon_get_clock_crystal_freq(struct radeon *radeon)
 
 static int radeon_get_num_backends(struct radeon *radeon)
 {
-       struct drm_radeon_info info;
-       uint32_t num_backends;
+       struct drm_radeon_info info = {};
+       uint32_t num_backends = 0;
        int r;
 
        info.request = RADEON_INFO_NUM_BACKENDS;
@@ -228,6 +259,42 @@ static int radeon_get_num_backends(struct radeon *radeon)
        return 0;
 }
 
+static int radeon_get_num_tile_pipes(struct radeon *radeon)
+{
+       struct drm_radeon_info info = {};
+       uint32_t num_tile_pipes = 0;
+       int r;
+
+       info.request = RADEON_INFO_NUM_TILE_PIPES;
+       info.value = (uintptr_t)&num_tile_pipes;
+       r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
+                       sizeof(struct drm_radeon_info));
+       if (r)
+               return r;
+
+       radeon->num_tile_pipes = num_tile_pipes;
+       return 0;
+}
+
+static int radeon_get_backend_map(struct radeon *radeon)
+{
+       struct drm_radeon_info info = {};
+       uint32_t backend_map = 0;
+       int r;
+
+       info.request = RADEON_INFO_BACKEND_MAP;
+       info.value = (uintptr_t)&backend_map;
+       r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
+                       sizeof(struct drm_radeon_info));
+       if (r)
+               return r;
+
+       radeon->backend_map = backend_map;
+       radeon->backend_map_valid = TRUE;
+
+       return 0;
+}
+
 
 static int radeon_init_fence(struct radeon *radeon)
 {
@@ -236,7 +303,7 @@ static int radeon_init_fence(struct radeon *radeon)
        if (radeon->fence_bo == NULL) {
                return -ENOMEM;
        }
-       radeon->cfence = r600_bo_map(radeon, radeon->fence_bo, PB_USAGE_UNSYNCHRONIZED, NULL);
+       radeon->cfence = r600_bo_map(radeon, radeon->fence_bo, PIPE_TRANSFER_UNSYNCHRONIZED, NULL);
        *radeon->cfence = 0;
        return 0;
 }
@@ -320,6 +387,8 @@ static struct radeon *radeon_new(int fd, unsigned device)
        case CHIP_CYPRESS:
        case CHIP_HEMLOCK:
        case CHIP_PALM:
+       case CHIP_SUMO:
+       case CHIP_SUMO2:
        case CHIP_BARTS:
        case CHIP_TURKS:
        case CHIP_CAICOS:
@@ -327,6 +396,11 @@ static struct radeon *radeon_new(int fd, unsigned device)
                /* set default group bytes, overridden by tiling info ioctl */
                radeon->tiling_info.group_bytes = 512;
                break;
+       case CHIP_CAYMAN:
+               radeon->chip_class = CAYMAN;
+               /* set default group bytes, overridden by tiling info ioctl */
+               radeon->tiling_info.group_bytes = 512;
+               break;
        default:
                fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
                        __func__, radeon->device);
@@ -342,6 +416,11 @@ static struct radeon *radeon_new(int fd, unsigned device)
        if (radeon->minor_version >= 9)
                radeon_get_num_backends(radeon);
 
+       if (radeon->minor_version >= 11) {
+               radeon_get_num_tile_pipes(radeon);
+               radeon_get_backend_map(radeon);
+       }
+
        radeon->bomgr = r600_bomgr_create(radeon, 1000000);
        if (radeon->bomgr == NULL) {
                return NULL;