#include <stdio.h>
#include "dev/gen_device_info.h"
#include "main/macros.h"
+#include "main/mtypes.h"
#include "util/ralloc.h"
#ifdef __cplusplus
uint8_t *ra_reg_to_grf;
/**
- * ra class for the aligned pairs we use for PLN, which doesn't
+ * ra class for the aligned barycentrics we use for PLN, which doesn't
* appear in *classes.
*/
- int aligned_pairs_class;
+ int aligned_bary_class;
} fs_reg_sets[3];
void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
- bool scalar_stage[MESA_SHADER_STAGES];
- struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
+ bool scalar_stage[MESA_ALL_SHADER_STAGES];
+ bool use_tcs_8_patch;
+ struct gl_shader_compiler_options glsl_compiler_options[MESA_ALL_SHADER_STAGES];
/**
* Apply workarounds for SIN and COS output range problems.
* will attempt to push everything.
*/
bool supports_pull_constants;
+
+ /**
+ * Whether or not the driver supports NIR shader constants. This controls
+ * whether nir_opt_large_constants will be run.
+ */
+ bool supports_shader_constants;
+
+ /**
+ * Whether or not the driver wants uniform params to be compacted by the
+ * back-end compiler.
+ */
+ bool compact_params;
+
+ /**
+ * Whether or not the driver wants variable group size to be lowered by the
+ * back-end compiler.
+ */
+ bool lower_variable_group_size;
};
+/**
+ * We use a constant subgroup size of 32. It really only needs to be a
+ * maximum and, since we do SIMD32 for compute shaders in some cases, it
+ * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
+ * subgroup size of 32 but will act as if 16 or 24 of those channels are
+ * disabled.
+ */
+#define BRW_SUBGROUP_SIZE 32
/**
* Program key structures.
uint32_t y_uv_image_mask;
uint32_t yx_xuxv_image_mask;
uint32_t xy_uxvx_image_mask;
+ uint32_t ayuv_image_mask;
+ uint32_t xyuv_image_mask;
+ uint32_t bt709_mask;
+ uint32_t bt2020_mask;
+
+ /* Scale factor for each texture. */
+ float scale_factors[32];
+};
+
+/** An enum representing what kind of input gl_SubgroupSize is. */
+enum PACKED brw_subgroup_size_type
+{
+ BRW_SUBGROUP_SIZE_API_CONSTANT, /**< Default Vulkan behavior */
+ BRW_SUBGROUP_SIZE_UNIFORM, /**< OpenGL behavior */
+ BRW_SUBGROUP_SIZE_VARYING, /**< VK_EXT_subgroup_size_control */
+
+ /* These enums are specifically chosen so that the value of the enum is
+ * also the subgroup size. If any new values are added, they must respect
+ * this invariant.
+ */
+ BRW_SUBGROUP_SIZE_REQUIRE_8 = 8, /**< VK_EXT_subgroup_size_control */
+ BRW_SUBGROUP_SIZE_REQUIRE_16 = 16, /**< VK_EXT_subgroup_size_control */
+ BRW_SUBGROUP_SIZE_REQUIRE_32 = 32, /**< VK_EXT_subgroup_size_control */
+};
+
+struct brw_base_prog_key {
+ unsigned program_string_id;
+
+ enum brw_subgroup_size_type subgroup_size_type;
+
+ struct brw_sampler_prog_key_data tex;
};
/**
/** The program key for Vertex Shaders. */
struct brw_vs_prog_key {
- unsigned program_string_id;
+ struct brw_base_prog_key base;
/**
* Per-attribute workaround flags
* the VUE, even if they aren't written by the vertex shader.
*/
uint8_t point_coord_replace;
-
- struct brw_sampler_prog_key_data tex;
};
/** The program key for Tessellation Control Shaders. */
struct brw_tcs_prog_key
{
- unsigned program_string_id;
+ struct brw_base_prog_key base;
GLenum tes_primitive_mode;
uint64_t outputs_written;
bool quads_workaround;
-
- struct brw_sampler_prog_key_data tex;
};
/** The program key for Tessellation Evaluation Shaders. */
struct brw_tes_prog_key
{
- unsigned program_string_id;
+ struct brw_base_prog_key base;
/** A bitfield of per-patch inputs read. */
uint32_t patch_inputs_read;
/** A bitfield of per-vertex inputs read. */
uint64_t inputs_read;
- struct brw_sampler_prog_key_data tex;
+ /**
+ * How many user clipping planes are being uploaded to the tessellation
+ * evaluation shader as push constants.
+ *
+ * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
+ * clip distances.
+ */
+ unsigned nr_userclip_plane_consts:4;
};
/** The program key for Geometry Shaders. */
struct brw_gs_prog_key
{
- unsigned program_string_id;
+ struct brw_base_prog_key base;
- struct brw_sampler_prog_key_data tex;
+ /**
+ * How many user clipping planes are being uploaded to the geometry shader
+ * as push constants.
+ *
+ * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
+ * clip distances.
+ */
+ unsigned nr_userclip_plane_consts:4;
};
enum brw_sf_primitive {
/** The program key for Fragment/Pixel Shaders. */
struct brw_wm_prog_key {
+ struct brw_base_prog_key base;
+
/* Some collection of BRW_WM_IZ_* */
uint8_t iz_lookup;
bool stats_wm:1;
bool flat_shade:1;
unsigned nr_color_regions:5;
- bool replicate_alpha:1;
+ bool alpha_test_replicate_alpha:1;
+ bool alpha_to_coverage:1;
bool clamp_fragment_color:1;
bool persample_interp:1;
bool multisample_fbo:1;
bool high_quality_derivatives:1;
bool force_dual_color_blend:1;
bool coherent_fb_fetch:1;
+ bool ignore_sample_mask_out:1;
+ uint8_t color_outputs_valid;
uint64_t input_slots_valid;
- unsigned program_string_id;
GLenum alpha_test_func; /* < For Gen4/5 MRT alpha test */
float alpha_test_ref;
-
- struct brw_sampler_prog_key_data tex;
};
struct brw_cs_prog_key {
- uint32_t program_string_id;
- struct brw_sampler_prog_key_data tex;
+ struct brw_base_prog_key base;
};
/* brw_any_prog_key is any of the keys that map to an API stage */
union brw_any_prog_key {
+ struct brw_base_prog_key base;
struct brw_vs_prog_key vs;
struct brw_tcs_prog_key tcs;
struct brw_tes_prog_key tes;
* entries [most of them except when we're doing untyped surface
* access] will be removed by the uniform packing pass.
*/
-#define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
-#define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
-#define BRW_IMAGE_PARAM_SIZE_OFFSET 8
-#define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
-#define BRW_IMAGE_PARAM_TILING_OFFSET 16
-#define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
-#define BRW_IMAGE_PARAM_SIZE 24
+#define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
+#define BRW_IMAGE_PARAM_SIZE_OFFSET 4
+#define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
+#define BRW_IMAGE_PARAM_TILING_OFFSET 12
+#define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
+#define BRW_IMAGE_PARAM_SIZE 20
struct brw_image_param {
- /** Surface binding table index. */
- uint32_t surface_idx;
-
/** Offset applied to the X and Y surface coordinates. */
uint32_t offset[2];
BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X,
BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y,
+ BRW_PARAM_BUILTIN_PATCH_VERTICES_IN,
+
+ BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X,
+ BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y,
+ BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z,
BRW_PARAM_BUILTIN_SUBGROUP_ID,
+ BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X,
+ BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Y,
+ BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z,
};
#define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
#define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
(((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
+/** Represents a code relocation
+ *
+ * Relocatable constants are immediates in the code which we want to be able
+ * to replace post-compile with the actual value.
+ */
+struct brw_shader_reloc {
+ /** The 32-bit ID of the relocatable constant */
+ uint32_t id;
+
+ /** The offset in the shader to the relocatable instruction
+ *
+ * This is the offset to the instruction rather than the immediate value
+ * itself. This allows us to do some sanity checking while we relocate.
+ */
+ uint32_t offset;
+};
+
+/** A value to write to a relocation */
+struct brw_shader_reloc_value {
+ /** The 32-bit ID of the relocatable constant */
+ uint32_t id;
+
+ /** The value with which to replace the relocated immediate */
+ uint32_t value;
+};
+
struct brw_stage_prog_data {
struct {
/** size of our binding table. */
GLuint nr_params; /**< number of float params/constants */
GLuint nr_pull_params;
+ /* zero_push_reg is a bitfield which indicates what push registers (if any)
+ * should be zeroed by SW at the start of the shader. The corresponding
+ * push_reg_mask_param specifies the param index (in 32-bit units) where
+ * the actual runtime 64-bit mask will be pushed. The shader will zero
+ * push reg i if
+ *
+ * reg_used & zero_push_reg & ~*push_reg_mask_param & (1ull << i)
+ *
+ * If this field is set, brw_compiler::compact_params must be false.
+ */
+ uint64_t zero_push_reg;
+ unsigned push_reg_mask_param;
+
unsigned curb_read_length;
unsigned total_scratch;
unsigned total_shared;
unsigned program_size;
+ unsigned const_data_size;
+ unsigned const_data_offset;
+
+ unsigned num_relocs;
+ const struct brw_shader_reloc *relocs;
+
+ /** Does this program pull from any UBO or other constant buffers? */
+ bool has_ubo_pull;
+
/**
* Register where the thread expects to find input data from the URB
* (typically uniforms, followed by vertex or fragment attributes).
*/
uint32_t *param;
uint32_t *pull_param;
+
+ /* Whether shader uses atomic operations. */
+ bool uses_atomic_load_store;
};
static inline uint32_t *
return prog_data->param + old_nr_params;
}
-static inline void
-brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
- unsigned surf_index)
-{
- /* A binding table index is 8 bits and the top 3 values are reserved for
- * special things (stateless and SLM).
- */
- assert(surf_index <= 252);
-
- prog_data->binding_table.size_bytes =
- MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
-}
-
enum brw_barycentric_mode {
BRW_BARYCENTRIC_PERSPECTIVE_PIXEL = 0,
BRW_BARYCENTRIC_PERSPECTIVE_CENTROID = 1,
GLuint num_varying_inputs;
- uint8_t reg_blocks_0;
- uint8_t reg_blocks_2;
+ uint8_t reg_blocks_8;
+ uint8_t reg_blocks_16;
+ uint8_t reg_blocks_32;
- uint8_t dispatch_grf_start_reg_2;
- uint32_t prog_offset_2;
+ uint8_t dispatch_grf_start_reg_16;
+ uint8_t dispatch_grf_start_reg_32;
+ uint32_t prog_offset_16;
+ uint32_t prog_offset_32;
struct {
/** @{
bool inner_coverage;
bool dispatch_8;
bool dispatch_16;
+ bool dispatch_32;
bool dual_src_blend;
bool persample_dispatch;
bool uses_pos_offset;
*/
uint32_t flat_inputs;
+ /**
+ * The FS inputs
+ */
+ uint64_t inputs;
+
/* Mapping of VUE slots to interpolation modes.
* Used by the Gen4-5 clip/sf/wm stages.
*/
* For varying slots that are not used by the FS, the value is -1.
*/
int urb_setup[VARYING_SLOT_MAX];
+
+ /**
+ * Cache structure into the urb_setup array above that contains the
+ * attribute numbers of active varyings out of urb_setup.
+ * The actual count is stored in urb_setup_attribs_count.
+ */
+ uint8_t urb_setup_attribs[VARYING_SLOT_MAX];
+ uint8_t urb_setup_attribs_count;
};
+/** Returns the SIMD width corresponding to a given KSP index
+ *
+ * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
+ * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
+ * kernel start pointer (KSP) indices that is based on what dispatch widths
+ * are enabled. This function provides, effectively, the reverse mapping.
+ *
+ * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
+ * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
+ */
+static inline unsigned
+brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled,
+ bool simd16_enabled, bool simd32_enabled)
+{
+ /* This function strictly ignores contiguous dispatch */
+ switch (ksp_idx) {
+ case 0:
+ return simd8_enabled ? 8 :
+ (simd16_enabled && !simd32_enabled) ? 16 :
+ (simd32_enabled && !simd16_enabled) ? 32 : 0;
+ case 1:
+ return (simd32_enabled && (simd16_enabled || simd8_enabled)) ? 32 : 0;
+ case 2:
+ return (simd16_enabled && (simd32_enabled || simd8_enabled)) ? 16 : 0;
+ default:
+ unreachable("Invalid KSP index");
+ }
+}
+
+#define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
+ brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
+ (wm_state)._16PixelDispatchEnable, \
+ (wm_state)._32PixelDispatchEnable)
+
+#define brw_wm_state_has_ksp(wm_state, ksp_idx) \
+ (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
+
+static inline uint32_t
+_brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data *prog_data,
+ unsigned simd_width)
+{
+ switch (simd_width) {
+ case 8: return 0;
+ case 16: return prog_data->prog_offset_16;
+ case 32: return prog_data->prog_offset_32;
+ default: return 0;
+ }
+}
+
+#define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
+ _brw_wm_prog_data_prog_offset(prog_data, \
+ brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
+
+static inline uint8_t
+_brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_data,
+ unsigned simd_width)
+{
+ switch (simd_width) {
+ case 8: return prog_data->base.dispatch_grf_start_reg;
+ case 16: return prog_data->dispatch_grf_start_reg_16;
+ case 32: return prog_data->dispatch_grf_start_reg_32;
+ default: return 0;
+ }
+}
+
+#define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
+ _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
+ brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
+
+static inline uint8_t
+_brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data *prog_data,
+ unsigned simd_width)
+{
+ switch (simd_width) {
+ case 8: return prog_data->reg_blocks_8;
+ case 16: return prog_data->reg_blocks_16;
+ case 32: return prog_data->reg_blocks_32;
+ default: return 0;
+ }
+}
+
+#define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
+ _brw_wm_prog_data_reg_blocks(prog_data, \
+ brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
+
struct brw_push_const_block {
unsigned dwords; /* Dword count, not reg aligned */
unsigned regs;
struct brw_stage_prog_data base;
unsigned local_size[3];
- unsigned simd_size;
- unsigned threads;
+ unsigned slm_size;
+
+ /* Program offsets for the 8/16/32 SIMD variants. Multiple variants are
+ * kept when using variable group size, and the right one can only be
+ * decided at dispatch time.
+ */
+ unsigned prog_offset[3];
+
+ /* Bitmask indicating which program offsets are valid. */
+ unsigned prog_mask;
+
+ /* Bitmask indicating which programs have spilled. */
+ unsigned prog_spilled;
+
bool uses_barrier;
bool uses_num_work_groups;
struct {
struct brw_push_const_block cross_thread;
struct brw_push_const_block per_thread;
- struct brw_push_const_block total;
} push;
struct {
} binding_table;
};
+static inline uint32_t
+brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data *prog_data,
+ unsigned dispatch_width)
+{
+ assert(dispatch_width == 8 ||
+ dispatch_width == 16 ||
+ dispatch_width == 32);
+ const unsigned index = dispatch_width / 16;
+ assert(prog_data->prog_mask & (1 << index));
+ return prog_data->prog_offset[index];
+}
+
/**
* Enum representing the i965-specific vertex results that don't correspond
* exactly to any element of gl_varying_slot. The values of this enum are
void brw_compute_vue_map(const struct gen_device_info *devinfo,
struct brw_vue_map *vue_map,
uint64_t slots_valid,
- bool separate_shader);
+ bool separate_shader,
+ uint32_t pos_slots);
void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
uint64_t slots_valid,
/* brw_interpolation_map.c */
void brw_setup_vue_interpolation(struct brw_vue_map *vue_map,
struct nir_shader *nir,
- struct brw_wm_prog_data *prog_data,
- const struct gen_device_info *devinfo);
+ struct brw_wm_prog_data *prog_data);
enum shader_dispatch_mode {
DISPATCH_MODE_4X1_SINGLE = 0,
DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
DISPATCH_MODE_SIMD8 = 3,
+
+ DISPATCH_MODE_TCS_SINGLE_PATCH = 0,
+ DISPATCH_MODE_TCS_8_PATCH = 2,
};
/**
bool uses_vertexid;
bool uses_instanceid;
- bool uses_basevertex;
+ bool uses_is_indexed_draw;
+ bool uses_firstvertex;
bool uses_baseinstance;
bool uses_drawid;
};
{
struct brw_vue_prog_data base;
+ /** Should the non-SINGLE_PATCH payload provide primitive ID? */
+ bool include_primitive_id;
+
/** Number vertices in output patch */
int instances;
+
+ /** Track patch count threshold */
+ int patch_count_threshold;
};
struct brw_cs_prog_data cs;
};
-#define DEFINE_PROG_DATA_DOWNCAST(stage) \
-static inline struct brw_##stage##_prog_data * \
-brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
-{ \
- return (struct brw_##stage##_prog_data *) prog_data; \
+#define DEFINE_PROG_DATA_DOWNCAST(stage) \
+static inline struct brw_##stage##_prog_data * \
+brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
+{ \
+ return (struct brw_##stage##_prog_data *) prog_data; \
+} \
+static inline const struct brw_##stage##_prog_data * \
+brw_##stage##_prog_data_const(const struct brw_stage_prog_data *prog_data) \
+{ \
+ return (const struct brw_##stage##_prog_data *) prog_data; \
}
DEFINE_PROG_DATA_DOWNCAST(vue)
DEFINE_PROG_DATA_DOWNCAST(vs)
DEFINE_PROG_DATA_DOWNCAST(sf)
#undef DEFINE_PROG_DATA_DOWNCAST
+struct brw_compile_stats {
+ uint32_t dispatch_width; /**< 0 for vec4 */
+ uint32_t instructions;
+ uint32_t sends;
+ uint32_t loops;
+ uint32_t cycles;
+ uint32_t spills;
+ uint32_t fills;
+};
+
/** @} */
struct brw_compiler *
brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo);
+/**
+ * Returns a compiler configuration for use with disk shader cache
+ *
+ * This value only needs to change for settings that can cause different
+ * program generation between two runs on the same hardware.
+ *
+ * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
+ * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
+ */
+uint64_t
+brw_get_compiler_config_value(const struct brw_compiler *compiler);
+
unsigned
brw_prog_data_size(gl_shader_stage stage);
unsigned
brw_prog_key_size(gl_shader_stage stage);
+void
+brw_prog_key_set_id(union brw_any_prog_key *key, gl_shader_stage, unsigned id);
+
/**
* Compile a vertex shader.
*
void *mem_ctx,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *prog_data,
- const struct nir_shader *shader,
+ struct nir_shader *shader,
int shader_time_index,
+ struct brw_compile_stats *stats,
char **error_str);
/**
void *mem_ctx,
const struct brw_tcs_prog_key *key,
struct brw_tcs_prog_data *prog_data,
- const struct nir_shader *nir,
+ struct nir_shader *nir,
int shader_time_index,
+ struct brw_compile_stats *stats,
char **error_str);
/**
const struct brw_tes_prog_key *key,
const struct brw_vue_map *input_vue_map,
struct brw_tes_prog_data *prog_data,
- const struct nir_shader *shader,
- struct gl_program *prog,
+ struct nir_shader *shader,
int shader_time_index,
+ struct brw_compile_stats *stats,
char **error_str);
/**
void *mem_ctx,
const struct brw_gs_prog_key *key,
struct brw_gs_prog_data *prog_data,
- const struct nir_shader *shader,
+ struct nir_shader *shader,
struct gl_program *prog,
int shader_time_index,
+ struct brw_compile_stats *stats,
char **error_str);
/**
void *mem_ctx,
const struct brw_wm_prog_key *key,
struct brw_wm_prog_data *prog_data,
- const struct nir_shader *shader,
- struct gl_program *prog,
+ struct nir_shader *shader,
int shader_time_index8,
int shader_time_index16,
+ int shader_time_index32,
bool allow_spilling,
bool use_rep_send, struct brw_vue_map *vue_map,
+ struct brw_compile_stats *stats, /**< Array of three stats */
char **error_str);
/**
struct brw_cs_prog_data *prog_data,
const struct nir_shader *shader,
int shader_time_index,
+ struct brw_compile_stats *stats,
char **error_str);
+void brw_debug_key_recompile(const struct brw_compiler *c, void *log,
+ gl_shader_stage stage,
+ const struct brw_base_prog_key *old_key,
+ const struct brw_base_prog_key *key);
+
static inline uint32_t
encode_slm_size(unsigned gen, uint32_t bytes)
{
return slm_size;
}
+unsigned
+brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data,
+ unsigned threads);
+
+unsigned
+brw_cs_simd_size_for_group_size(const struct gen_device_info *devinfo,
+ const struct brw_cs_prog_data *cs_prog_data,
+ unsigned group_size);
+
+void
+brw_write_shader_relocs(const struct gen_device_info *devinfo,
+ void *program,
+ const struct brw_stage_prog_data *prog_data,
+ struct brw_shader_reloc_value *values,
+ unsigned num_values);
+
+/**
+ * Calculate the RightExecutionMask field used in GPGPU_WALKER.
+ */
+static inline unsigned
+brw_cs_right_mask(unsigned group_size, unsigned simd_size)
+{
+ const uint32_t remainder = group_size & (simd_size - 1);
+ if (remainder > 0)
+ return ~0u >> (32 - remainder);
+ else
+ return ~0u >> (32 - simd_size);
+}
+
/**
* Return true if the given shader stage is dispatched contiguously by the
* relevant fixed function starting from channel 0 of the SIMD thread, which
* '2^n - 1' for some n.
*/
static inline bool
-brw_stage_has_packed_dispatch(MAYBE_UNUSED const struct gen_device_info *devinfo,
+brw_stage_has_packed_dispatch(ASSERTED const struct gen_device_info *devinfo,
gl_shader_stage stage,
const struct brw_stage_prog_data *prog_data)
{
* to do a full test run with brw_fs_test_dispatch_packing() hooked up to
* the NIR front-end before changing this assertion.
*/
- assert(devinfo->gen <= 10);
+ assert(devinfo->gen <= 12);
switch (stage) {
case MESA_SHADER_FRAGMENT: {
projects / mesa.git / blobdiff