intel/ir: Remove scheduling-based cycle count estimates.
[mesa.git] / src / intel / compiler / brw_fs_reg_allocate.cpp
index 9e6e414d104cf4c9ad6a6818c27747f54b95db43..ee758009cadba0d861b4bfc5e0ad35197ef244ac 100644 (file)
@@ -86,7 +86,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
 {
    const struct gen_device_info *devinfo = compiler->devinfo;
    int base_reg_count = BRW_MAX_GRF;
-   const int index = _mesa_logbase2(dispatch_width / 8);
+   const int index = util_logbase2(dispatch_width / 8);
 
    if (dispatch_width > 8 && devinfo->gen >= 7) {
       /* For IVB+, we don't need the PLN hacks or the even-reg alignment in
@@ -331,7 +331,7 @@ count_to_loop_end(const bblock_t *block)
 }
 
 void fs_visitor::calculate_payload_ranges(int payload_node_count,
-                                          int *payload_last_use_ip)
+                                          int *payload_last_use_ip) const
 {
    int loop_depth = 0;
    int loop_end_ip = 0;
@@ -410,7 +410,8 @@ void fs_visitor::calculate_payload_ranges(int payload_node_count,
 class fs_reg_alloc {
 public:
    fs_reg_alloc(fs_visitor *fs):
-      fs(fs), devinfo(fs->devinfo), compiler(fs->compiler), g(NULL),
+      fs(fs), devinfo(fs->devinfo), compiler(fs->compiler),
+      live(fs->live_analysis.require()), g(NULL),
       have_spill_costs(false)
    {
       mem_ctx = ralloc_context(NULL);
@@ -422,7 +423,7 @@ public:
        * for reg_width == 2.
        */
       int reg_width = fs->dispatch_width / 8;
-      rsi = _mesa_logbase2(reg_width);
+      rsi = util_logbase2(reg_width);
       payload_node_count = ALIGN(fs->first_non_payload_grf, reg_width);
 
       /* Get payload IP information */
@@ -443,7 +444,7 @@ public:
 private:
    void setup_live_interference(unsigned node,
                                 int node_start_ip, int node_end_ip);
-   void setup_inst_interference(fs_inst *inst);
+   void setup_inst_interference(const fs_inst *inst);
 
    void build_interference_graph(bool allow_spilling);
    void discard_interference_graph();
@@ -457,6 +458,7 @@ private:
    fs_visitor *fs;
    const gen_device_info *devinfo;
    const brw_compiler *compiler;
+   const fs_live_variables &live;
 
    /* Which compiler->fs_reg_sets[] to use */
    int rsi;
@@ -488,7 +490,7 @@ private:
  * contents.
  */
 static void
-get_used_mrfs(fs_visitor *v, bool *mrf_used)
+get_used_mrfs(const fs_visitor *v, bool *mrf_used)
 {
    int reg_width = v->dispatch_width / 8;
 
@@ -590,14 +592,14 @@ fs_reg_alloc::setup_live_interference(unsigned node,
    for (unsigned n2 = first_vgrf_node;
         n2 < (unsigned)first_spill_node && n2 < node; n2++) {
       unsigned vgrf = n2 - first_vgrf_node;
-      if (!(node_end_ip <= fs->live_intervals->vgrf_start[vgrf] ||
-            fs->live_intervals->vgrf_end[vgrf] <= node_start_ip))
+      if (!(node_end_ip <= live.vgrf_start[vgrf] ||
+            live.vgrf_end[vgrf] <= node_start_ip))
          ra_add_node_interference(g, node, n2);
    }
 }
 
 void
-fs_reg_alloc::setup_inst_interference(fs_inst *inst)
+fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
 {
    /* Certain instructions can't safely use the same register for their
     * sources and destination.  Add interference.
@@ -717,9 +719,6 @@ fs_reg_alloc::setup_inst_interference(fs_inst *inst)
 void
 fs_reg_alloc::build_interference_graph(bool allow_spilling)
 {
-   const gen_device_info *devinfo = fs->devinfo;
-   const brw_compiler *compiler = fs->compiler;
-
    /* Compute the RA node layout */
    node_count = 0;
    first_payload_node = node_count;
@@ -740,7 +739,6 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
    node_count += fs->alloc.count;
    first_spill_node = node_count;
 
-   fs->calculate_live_intervals();
    fs->calculate_payload_ranges(payload_node_count,
                                 payload_last_use_ip);
 
@@ -812,8 +810,8 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
    /* Add interference based on the live range of the register */
    for (unsigned i = 0; i < fs->alloc.count; i++) {
       setup_live_interference(first_vgrf_node + i,
-                              fs->live_intervals->vgrf_start[i],
-                              fs->live_intervals->vgrf_end[i]);
+                              live.vgrf_start[i],
+                              live.vgrf_end[i]);
    }
 
    /* Add interference based on the instructions in which a register is used.
@@ -953,7 +951,7 @@ fs_reg_alloc::set_spill_costs()
       if (no_spill[i])
          continue;
 
-      int live_length = fs->live_intervals->vgrf_end[i] - fs->live_intervals->vgrf_start[i];
+      int live_length = live.vgrf_end[i] - live.vgrf_start[i];
       if (live_length <= 0)
          continue;