if (mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE)
*mask |= BRW_CR0_FP_MODE_MASK;
+ if (*mask != 0)
+ assert((*mask & brw_mode) == brw_mode);
+
return brw_mode;
}
return;
fs_builder abld = bld.annotate("shader floats control execution mode");
- unsigned mask = 0;
- unsigned mode = brw_rnd_mode_from_nir(execution_mode, &mask);
+ unsigned mask, mode = brw_rnd_mode_from_nir(execution_mode, &mask);
+
+ if (mask == 0)
+ return;
+
abld.emit(SHADER_OPCODE_FLOAT_CONTROL_MODE, bld.null_reg_ud(),
brw_imm_d(mode), brw_imm_d(mask));
}
* XXX - Emit an extra single-source NULL RT-write marked LastRT in
* order to release the thread dependency without disabling
* SIMD32.
+ *
+ * The dual-source RT write messages may lead to hangs with SIMD16
+ * dispatch on ICL due some unknown reasons, see
+ * https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183
*/
- limit_dispatch_width(16, "Dual source blending unsupported "
- "in SIMD32 mode.\n");
+ limit_dispatch_width(8, "Dual source blending unsupported "
+ "in SIMD16 and SIMD32 modes.\n");
}
}
key(key), gs_compile(NULL), prog_data(prog_data),
input_vue_map(input_vue_map),
live_analysis(this), regpressure_analysis(this),
+ performance_analysis(this),
dispatch_width(dispatch_width),
shader_time_index(shader_time_index),
bld(fs_builder(this, dispatch_width).at_end())
key(&c->key.base), gs_compile(c),
prog_data(&prog_data->base.base),
live_analysis(this), regpressure_analysis(this),
+ performance_analysis(this),
dispatch_width(8),
shader_time_index(shader_time_index),
bld(fs_builder(this, dispatch_width).at_end())