/* Sample from the MCS surface attached to this multisample texture. */
fs_reg
fs_visitor::emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
- const fs_reg &texture)
+ const fs_reg &texture,
+ const fs_reg &texture_handle)
{
const fs_reg dest = vgrf(glsl_type::uvec4_type);
fs_reg srcs[TEX_LOGICAL_NUM_SRCS];
srcs[TEX_LOGICAL_SRC_COORDINATE] = coordinate;
srcs[TEX_LOGICAL_SRC_SURFACE] = texture;
- srcs[TEX_LOGICAL_SRC_SAMPLER] = texture;
+ srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_ud(0);
+ srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE] = texture_handle;
srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(components);
srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(0);
fs_inst *write;
write = bld.emit(FS_OPCODE_FB_WRITE);
write->eot = true;
+ write->last_rt = true;
if (devinfo->gen >= 6) {
write->base_mrf = 2;
write->mlen = 4 * reg_width;
wm_prog_data->num_varying_inputs = devinfo->gen < 6 ? 1 : 0;
memset(wm_prog_data->urb_setup, -1,
sizeof(wm_prog_data->urb_setup[0]) * VARYING_SLOT_MAX);
+ brw_compute_urb_setup_index(wm_prog_data);
/* We don't have any uniforms. */
stage_prog_data->nr_params = 0;
stage_prog_data->nr_pull_params = 0;
stage_prog_data->curb_read_length = 0;
stage_prog_data->dispatch_grf_start_reg = 2;
- wm_prog_data->dispatch_grf_start_reg_2 = 2;
+ wm_prog_data->dispatch_grf_start_reg_16 = 2;
+ wm_prog_data->dispatch_grf_start_reg_32 = 2;
grf_used = 1; /* Gen4-5 don't allow zero GRF blocks */
calculate_cfg();
* data. It will get adjusted to be a real location before
* generate_code() time.
*/
-struct brw_reg
+fs_reg
fs_visitor::interp_reg(int location, int channel)
{
assert(stage == MESA_SHADER_FRAGMENT);
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
- int regnr = prog_data->urb_setup[location] * 2 + channel / 2;
- int stride = (channel & 1) * 4;
-
+ int regnr = prog_data->urb_setup[location] * 4 + channel;
assert(prog_data->urb_setup[location] != -1);
- return brw_vec1_grf(regnr, stride);
+ return fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_F);
}
/** Emits the interpolation for the varying inputs. */
const fs_reg xstart(negate(brw_vec1_grf(1, 0)));
const fs_reg ystart(negate(brw_vec1_grf(1, 1)));
- if (devinfo->has_pln && dispatch_width == 16) {
- for (unsigned i = 0; i < 2; i++) {
- abld.half(i).ADD(half(offset(delta_xy, abld, i), 0),
- half(this->pixel_x, i), xstart);
- abld.half(i).ADD(half(offset(delta_xy, abld, i), 1),
- half(this->pixel_y, i), ystart);
+ if (devinfo->has_pln) {
+ for (unsigned i = 0; i < dispatch_width / 8; i++) {
+ abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 0), i),
+ quarter(this->pixel_x, i), xstart);
+ abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 1), i),
+ quarter(this->pixel_y, i), ystart);
}
} else {
abld.ADD(offset(delta_xy, abld, 0), this->pixel_x, xstart);
*/
this->wpos_w = vgrf(glsl_type::float_type);
abld.emit(FS_OPCODE_LINTERP, wpos_w, delta_xy,
- interp_reg(VARYING_SLOT_POS, 3));
+ component(interp_reg(VARYING_SLOT_POS, 3), 0));
/* Compute the pixel 1/W value from wpos.w. */
this->pixel_w = vgrf(glsl_type::float_type);
abld.emit(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
}
+static unsigned
+brw_rnd_mode_from_nir(unsigned mode, unsigned *mask)
+{
+ unsigned brw_mode = 0;
+ *mask = 0;
+
+ if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 |
+ FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 |
+ FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64) &
+ mode) {
+ brw_mode |= BRW_RND_MODE_RTZ << BRW_CR0_RND_MODE_SHIFT;
+ *mask |= BRW_CR0_RND_MODE_MASK;
+ }
+ if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 |
+ FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32 |
+ FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64) &
+ mode) {
+ brw_mode |= BRW_RND_MODE_RTNE << BRW_CR0_RND_MODE_SHIFT;
+ *mask |= BRW_CR0_RND_MODE_MASK;
+ }
+ if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP16) {
+ brw_mode |= BRW_CR0_FP16_DENORM_PRESERVE;
+ *mask |= BRW_CR0_FP16_DENORM_PRESERVE;
+ }
+ if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP32) {
+ brw_mode |= BRW_CR0_FP32_DENORM_PRESERVE;
+ *mask |= BRW_CR0_FP32_DENORM_PRESERVE;
+ }
+ if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP64) {
+ brw_mode |= BRW_CR0_FP64_DENORM_PRESERVE;
+ *mask |= BRW_CR0_FP64_DENORM_PRESERVE;
+ }
+ if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16)
+ *mask |= BRW_CR0_FP16_DENORM_PRESERVE;
+ if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32)
+ *mask |= BRW_CR0_FP32_DENORM_PRESERVE;
+ if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64)
+ *mask |= BRW_CR0_FP64_DENORM_PRESERVE;
+ if (mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE)
+ *mask |= BRW_CR0_FP_MODE_MASK;
+
+ if (*mask != 0)
+ assert((*mask & brw_mode) == brw_mode);
+
+ return brw_mode;
+}
+
+void
+fs_visitor::emit_shader_float_controls_execution_mode()
+{
+ unsigned execution_mode = this->nir->info.float_controls_execution_mode;
+ if (execution_mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE)
+ return;
+
+ fs_builder abld = bld.annotate("shader floats control execution mode");
+ unsigned mask, mode = brw_rnd_mode_from_nir(execution_mode, &mask);
+
+ if (mask == 0)
+ return;
+
+ abld.emit(SHADER_OPCODE_FLOAT_CONTROL_MODE, bld.null_reg_ud(),
+ brw_imm_d(mode), brw_imm_d(mask));
+}
+
/** Emits the interpolation for the varying inputs. */
void
fs_visitor::emit_interpolation_setup_gen6()
{
- struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
-
fs_builder abld = bld.annotate("compute pixel centers");
- if (devinfo->gen >= 8 || dispatch_width == 8) {
- /* The "Register Region Restrictions" page says for BDW (and newer,
- * presumably):
- *
- * "When destination spans two registers, the source may be one or
- * two registers. The destination elements must be evenly split
- * between the two registers."
- *
- * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
- * compute our pixel centers.
- */
- fs_reg int_pixel_xy(VGRF, alloc.allocate(dispatch_width / 8),
- BRW_REGISTER_TYPE_UW);
-
- const fs_builder dbld = abld.exec_all().group(dispatch_width * 2, 0);
- dbld.ADD(int_pixel_xy,
- fs_reg(stride(suboffset(g1_uw, 4), 1, 4, 0)),
- fs_reg(brw_imm_v(0x11001010)));
-
- this->pixel_x = vgrf(glsl_type::float_type);
- this->pixel_y = vgrf(glsl_type::float_type);
- abld.emit(FS_OPCODE_PIXEL_X, this->pixel_x, int_pixel_xy);
- abld.emit(FS_OPCODE_PIXEL_Y, this->pixel_y, int_pixel_xy);
- } else {
- /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
- *
- * "When destination spans two registers, the source MUST span two
- * registers."
- *
- * Since the GRF source of the ADD will only read a single register, we
- * must do two separate ADDs in SIMD16.
- */
- fs_reg int_pixel_x = vgrf(glsl_type::uint_type);
- fs_reg int_pixel_y = vgrf(glsl_type::uint_type);
- int_pixel_x.type = BRW_REGISTER_TYPE_UW;
- int_pixel_y.type = BRW_REGISTER_TYPE_UW;
- abld.ADD(int_pixel_x,
- fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
- fs_reg(brw_imm_v(0x10101010)));
- abld.ADD(int_pixel_y,
- fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
- fs_reg(brw_imm_v(0x11001100)));
-
- /* As of gen6, we can no longer mix float and int sources. We have
- * to turn the integer pixel centers into floats for their actual
- * use.
- */
- this->pixel_x = vgrf(glsl_type::float_type);
- this->pixel_y = vgrf(glsl_type::float_type);
- abld.MOV(this->pixel_x, int_pixel_x);
- abld.MOV(this->pixel_y, int_pixel_y);
+
+ this->pixel_x = vgrf(glsl_type::float_type);
+ this->pixel_y = vgrf(glsl_type::float_type);
+
+ for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
+ const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
+ struct brw_reg gi_uw = retype(brw_vec1_grf(1 + i, 0), BRW_REGISTER_TYPE_UW);
+
+ if (devinfo->gen >= 8 || dispatch_width == 8) {
+ /* The "Register Region Restrictions" page says for BDW (and newer,
+ * presumably):
+ *
+ * "When destination spans two registers, the source may be one or
+ * two registers. The destination elements must be evenly split
+ * between the two registers."
+ *
+ * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16
+ * to compute our pixel centers.
+ */
+ const fs_builder dbld =
+ abld.exec_all().group(hbld.dispatch_width() * 2, 0);
+ fs_reg int_pixel_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW);
+
+ dbld.ADD(int_pixel_xy,
+ fs_reg(stride(suboffset(gi_uw, 4), 1, 4, 0)),
+ fs_reg(brw_imm_v(0x11001010)));
+
+ hbld.emit(FS_OPCODE_PIXEL_X, offset(pixel_x, hbld, i), int_pixel_xy);
+ hbld.emit(FS_OPCODE_PIXEL_Y, offset(pixel_y, hbld, i), int_pixel_xy);
+ } else {
+ /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
+ *
+ * "When destination spans two registers, the source MUST span
+ * two registers."
+ *
+ * Since the GRF source of the ADD will only read a single register,
+ * we must do two separate ADDs in SIMD16.
+ */
+ const fs_reg int_pixel_x = hbld.vgrf(BRW_REGISTER_TYPE_UW);
+ const fs_reg int_pixel_y = hbld.vgrf(BRW_REGISTER_TYPE_UW);
+
+ hbld.ADD(int_pixel_x,
+ fs_reg(stride(suboffset(gi_uw, 4), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x10101010)));
+ hbld.ADD(int_pixel_y,
+ fs_reg(stride(suboffset(gi_uw, 5), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x11001100)));
+
+ /* As of gen6, we can no longer mix float and int sources. We have
+ * to turn the integer pixel centers into floats for their actual
+ * use.
+ */
+ hbld.MOV(offset(pixel_x, hbld, i), int_pixel_x);
+ hbld.MOV(offset(pixel_y, hbld, i), int_pixel_y);
+ }
}
abld = bld.annotate("compute pos.w");
- this->pixel_w = fs_reg(brw_vec8_grf(payload.source_w_reg, 0));
+ this->pixel_w = fetch_payload_reg(abld, payload.source_w_reg);
this->wpos_w = vgrf(glsl_type::float_type);
abld.emit(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(prog_data);
+
+ for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
+ this->delta_xy[i] = fetch_barycentric_reg(
+ bld, payload.barycentric_coord_reg[i]);
+ }
+
uint32_t centroid_modes = wm_prog_data->barycentric_interp_modes &
(1 << BRW_BARYCENTRIC_PERSPECTIVE_CENTROID |
1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID);
- for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
- uint8_t reg = payload.barycentric_coord_reg[i];
- this->delta_xy[i] = fs_reg(brw_vec16_grf(reg, 0));
-
- if (devinfo->needs_unlit_centroid_workaround &&
- (centroid_modes & (1 << i))) {
- /* Get the pixel/sample mask into f0 so that we know which
- * pixels are lit. Then, for each channel that is unlit,
- * replace the centroid data with non-centroid data.
- */
- bld.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
-
- uint8_t pixel_reg = payload.barycentric_coord_reg[i - 1];
-
- set_predicate_inv(BRW_PREDICATE_NORMAL, true,
- bld.half(0).MOV(brw_vec8_grf(reg, 0),
- brw_vec8_grf(pixel_reg, 0)));
- set_predicate_inv(BRW_PREDICATE_NORMAL, true,
- bld.half(0).MOV(brw_vec8_grf(reg + 1, 0),
- brw_vec8_grf(pixel_reg + 1, 0)));
- if (dispatch_width == 16) {
- set_predicate_inv(BRW_PREDICATE_NORMAL, true,
- bld.half(1).MOV(brw_vec8_grf(reg + 2, 0),
- brw_vec8_grf(pixel_reg + 2, 0)));
- set_predicate_inv(BRW_PREDICATE_NORMAL, true,
- bld.half(1).MOV(brw_vec8_grf(reg + 3, 0),
- brw_vec8_grf(pixel_reg + 3, 0)));
+ if (devinfo->needs_unlit_centroid_workaround && centroid_modes) {
+ /* Get the pixel/sample mask into f0 so that we know which
+ * pixels are lit. Then, for each channel that is unlit,
+ * replace the centroid data with non-centroid data.
+ */
+ for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
+ bld.exec_all().group(1, 0)
+ .MOV(retype(brw_flag_reg(0, i), BRW_REGISTER_TYPE_UW),
+ retype(brw_vec1_grf(1 + i, 7), BRW_REGISTER_TYPE_UW));
+ }
+
+ for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
+ if (!(centroid_modes & (1 << i)))
+ continue;
+
+ const fs_reg centroid_delta_xy = delta_xy[i];
+ const fs_reg &pixel_delta_xy = delta_xy[i - 1];
+
+ delta_xy[i] = bld.vgrf(BRW_REGISTER_TYPE_F, 2);
+
+ for (unsigned c = 0; c < 2; c++) {
+ for (unsigned q = 0; q < dispatch_width / 8; q++) {
+ set_predicate(BRW_PREDICATE_NORMAL,
+ bld.quarter(q).SEL(
+ quarter(offset(delta_xy[i], bld, c), q),
+ quarter(offset(centroid_delta_xy, bld, c), q),
+ quarter(offset(pixel_delta_xy, bld, c), q)));
+ }
}
- assert(dispatch_width != 32); /* not implemented yet */
}
}
}
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
/* Hand over gl_FragDepth or the payload depth. */
- const fs_reg dst_depth = (payload.dest_depth_reg ?
- fs_reg(brw_vec8_grf(payload.dest_depth_reg, 0)) :
- fs_reg());
+ const fs_reg dst_depth = fetch_payload_reg(bld, payload.dest_depth_reg);
fs_reg src_depth, src_stencil;
if (source_depth_to_render_target) {
if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
src_depth = frag_depth;
else
- src_depth = fs_reg(brw_vec8_grf(payload.source_depth_reg, 0));
+ src_depth = fetch_payload_reg(bld, payload.source_depth_reg);
}
if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL))
if (prog_data->uses_kill) {
write->predicate = BRW_PREDICATE_NORMAL;
- write->flag_subreg = 1;
+ write->flag_subreg = sample_mask_flag_subreg(this);
}
return write;
"in SIMD16+ mode.\n");
}
+ /* ANV doesn't know about sample mask output during the wm key creation
+ * so we compute if we need replicate alpha and emit alpha to coverage
+ * workaround here.
+ */
+ const bool replicate_alpha = key->alpha_test_replicate_alpha ||
+ (key->nr_color_regions > 1 && key->alpha_to_coverage &&
+ (sample_mask.file == BAD_FILE || devinfo->gen == 6));
+
for (int target = 0; target < key->nr_color_regions; target++) {
/* Skip over outputs that weren't written. */
if (this->outputs[target].file == BAD_FILE)
ralloc_asprintf(this->mem_ctx, "FB write target %d", target));
fs_reg src0_alpha;
- if (devinfo->gen >= 6 && key->replicate_alpha && target != 0)
+ if (devinfo->gen >= 6 && replicate_alpha && target != 0)
src0_alpha = offset(outputs[0], bld, 3);
inst = emit_single_fb_write(abld, this->outputs[target],
inst->target = target;
}
- prog_data->dual_src_blend = (this->dual_src_output.file != BAD_FILE);
+ prog_data->dual_src_blend = (this->dual_src_output.file != BAD_FILE &&
+ this->outputs[0].file != BAD_FILE);
assert(!prog_data->dual_src_blend || key->nr_color_regions == 1);
if (inst == NULL) {
inst->target = 0;
}
+ inst->last_rt = true;
inst->eot = true;
-}
-void
-fs_visitor::setup_uniform_clipplane_values()
-{
- const struct brw_vs_prog_key *key =
- (const struct brw_vs_prog_key *) this->key;
-
- if (key->nr_userclip_plane_consts == 0)
- return;
-
- assert(stage_prog_data->nr_params == uniforms);
- brw_stage_prog_data_add_params(stage_prog_data,
- key->nr_userclip_plane_consts * 4);
-
- for (int i = 0; i < key->nr_userclip_plane_consts; i++) {
- this->userplane[i] = fs_reg(UNIFORM, uniforms);
- for (int j = 0; j < 4; ++j) {
- stage_prog_data->param[uniforms + j] =
- BRW_PARAM_BUILTIN_CLIP_PLANE(i, j);
- }
- uniforms += 4;
- }
-}
-
-/**
- * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
- *
- * This does nothing if the shader uses gl_ClipDistance or user clipping is
- * disabled altogether.
- */
-void fs_visitor::compute_clip_distance()
-{
- struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data);
- const struct brw_vs_prog_key *key =
- (const struct brw_vs_prog_key *) this->key;
-
- /* Bail unless some sort of legacy clipping is enabled */
- if (key->nr_userclip_plane_consts == 0)
- return;
-
- /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
- *
- * "If a linked set of shaders forming the vertex stage contains no
- * static write to gl_ClipVertex or gl_ClipDistance, but the
- * application has requested clipping against user clip planes through
- * the API, then the coordinate written to gl_Position is used for
- * comparison against the user clip planes."
- *
- * This function is only called if the shader didn't write to
- * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
- * if the user wrote to it; otherwise we use gl_Position.
- */
-
- gl_varying_slot clip_vertex = VARYING_SLOT_CLIP_VERTEX;
- if (!(vue_prog_data->vue_map.slots_valid & VARYING_BIT_CLIP_VERTEX))
- clip_vertex = VARYING_SLOT_POS;
-
- /* If the clip vertex isn't written, skip this. Typically this means
- * the GS will set up clipping. */
- if (outputs[clip_vertex].file == BAD_FILE)
- return;
-
- setup_uniform_clipplane_values();
-
- const fs_builder abld = bld.annotate("user clip distances");
-
- this->outputs[VARYING_SLOT_CLIP_DIST0] = vgrf(glsl_type::vec4_type);
- this->outputs[VARYING_SLOT_CLIP_DIST1] = vgrf(glsl_type::vec4_type);
-
- for (int i = 0; i < key->nr_userclip_plane_consts; i++) {
- fs_reg u = userplane[i];
- const fs_reg output = offset(outputs[VARYING_SLOT_CLIP_DIST0 + i / 4],
- bld, i & 3);
-
- abld.MUL(output, outputs[clip_vertex], u);
- for (int j = 1; j < 4; j++) {
- u.nr = userplane[i].nr + j;
- abld.MAD(output, output, offset(outputs[clip_vertex], bld, j), u);
- }
+ if (devinfo->gen >= 11 && devinfo->gen <= 12 &&
+ prog_data->dual_src_blend) {
+ /* The dual-source RT write messages fail to release the thread
+ * dependency on ICL and TGL with SIMD32 dispatch, leading to hangs.
+ *
+ * XXX - Emit an extra single-source NULL RT-write marked LastRT in
+ * order to release the thread dependency without disabling
+ * SIMD32.
+ *
+ * The dual-source RT write messages may lead to hangs with SIMD16
+ * dispatch on ICL due some unknown reasons, see
+ * https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183
+ */
+ limit_dispatch_width(8, "Dual source blending unsupported "
+ "in SIMD16 and SIMD32 modes.\n");
}
}
per_slot_offsets = brw_imm_ud(output_vertex_size_owords *
gs_vertex_count.ud);
} else {
- per_slot_offsets = vgrf(glsl_type::int_type);
+ per_slot_offsets = vgrf(glsl_type::uint_type);
bld.MUL(per_slot_offsets, gs_vertex_count,
brw_imm_ud(output_vertex_size_owords));
}
sources[length++] = reg;
}
} else {
- for (unsigned i = 0; i < 4; i++)
- sources[length++] = offset(this->outputs[varying], bld, i);
+ int slot_offset = 0;
+
+ /* When using Primitive Replication, there may be multiple slots
+ * assigned to POS.
+ */
+ if (varying == VARYING_SLOT_POS)
+ slot_offset = slot - vue_map->varying_to_slot[VARYING_SLOT_POS];
+
+ for (unsigned i = 0; i < 4; i++) {
+ sources[length++] = offset(this->outputs[varying], bld,
+ i + (slot_offset * 4));
+ }
}
break;
}
header_size);
fs_inst *inst = abld.emit(opcode, reg_undef, payload);
- inst->eot = slot == last_slot && stage != MESA_SHADER_GEOMETRY;
+
+ /* For ICL WA 1805992985 one needs additional write in the end. */
+ if (devinfo->gen == 11 && stage == MESA_SHADER_TESS_EVAL)
+ inst->eot = false;
+ else
+ inst->eot = slot == last_slot && stage != MESA_SHADER_GEOMETRY;
+
inst->mlen = length + header_size;
inst->offset = urb_offset;
urb_offset = starting_urb_offset + slot + 1;
inst->mlen = 2;
inst->offset = 1;
return;
+ }
+
+ /* ICL WA 1805992985:
+ *
+ * ICLLP GPU hangs on one of tessellation vkcts tests with DS not done. The
+ * send cycle, which is a urb write with an eot must be 4 phases long and
+ * all 8 lanes must valid.
+ */
+ if (devinfo->gen == 11 && stage == MESA_SHADER_TESS_EVAL) {
+ fs_reg payload = fs_reg(VGRF, alloc.allocate(6), BRW_REGISTER_TYPE_UD);
+
+ /* Workaround requires all 8 channels (lanes) to be valid. This is
+ * understood to mean they all need to be alive. First trick is to find
+ * a live channel and copy its urb handle for all the other channels to
+ * make sure all handles are valid.
+ */
+ bld.exec_all().MOV(payload, bld.emit_uniformize(urb_handle));
+
+ /* Second trick is to use masked URB write where one can tell the HW to
+ * actually write data only for selected channels even though all are
+ * active.
+ * Third trick is to take advantage of the must-be-zero (MBZ) area in
+ * the very beginning of the URB.
+ *
+ * One masks data to be written only for the first channel and uses
+ * offset zero explicitly to land data to the MBZ area avoiding trashing
+ * any other part of the URB.
+ *
+ * Since the WA says that the write needs to be 4 phases long one uses
+ * 4 slots data. All are explicitly zeros in order to to keep the MBZ
+ * area written as zeros.
+ */
+ bld.exec_all().MOV(offset(payload, bld, 1), brw_imm_ud(0x10000u));
+ bld.exec_all().MOV(offset(payload, bld, 2), brw_imm_ud(0u));
+ bld.exec_all().MOV(offset(payload, bld, 3), brw_imm_ud(0u));
+ bld.exec_all().MOV(offset(payload, bld, 4), brw_imm_ud(0u));
+ bld.exec_all().MOV(offset(payload, bld, 5), brw_imm_ud(0u));
+
+ fs_inst *inst = bld.exec_all().emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
+ reg_undef, payload);
+ inst->eot = true;
+ inst->mlen = 6;
+ inst->offset = 0;
}
}
void
fs_visitor::emit_barrier()
{
- assert(devinfo->gen >= 7);
- const uint32_t barrier_id_mask =
- devinfo->gen >= 9 ? 0x8f000000u : 0x0f000000u;
+ uint32_t barrier_id_mask;
+ switch (devinfo->gen) {
+ case 7:
+ case 8:
+ barrier_id_mask = 0x0f000000u; break;
+ case 9:
+ case 10:
+ barrier_id_mask = 0x8f000000u; break;
+ case 11:
+ case 12:
+ barrier_id_mask = 0x7f000000u; break;
+ default:
+ unreachable("barrier is only available on gen >= 7");
+ }
/* We are getting the barrier ID from the compute shader header */
assert(stage == MESA_SHADER_COMPUTE);
fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
- const fs_builder pbld = bld.exec_all().group(8, 0);
-
/* Clear the message payload */
- pbld.MOV(payload, brw_imm_ud(0u));
+ bld.exec_all().group(8, 0).MOV(payload, brw_imm_ud(0u));
/* Copy the barrier id from r0.2 to the message payload reg.2 */
fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD));
- pbld.AND(component(payload, 2), r0_2, brw_imm_ud(barrier_id_mask));
+ bld.exec_all().group(1, 0).AND(component(payload, 2), r0_2,
+ brw_imm_ud(barrier_id_mask));
/* Emit a gateway "barrier" message using the payload we set up, followed
* by a wait instruction.
fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
- const void *key,
+ const brw_base_prog_key *key,
struct brw_stage_prog_data *prog_data,
- struct gl_program *prog,
const nir_shader *shader,
unsigned dispatch_width,
int shader_time_index,
const struct brw_vue_map *input_vue_map)
: backend_shader(compiler, log_data, mem_ctx, shader, prog_data),
- key(key), gs_compile(NULL), prog_data(prog_data), prog(prog),
+ key(key), gs_compile(NULL), prog_data(prog_data),
input_vue_map(input_vue_map),
+ live_analysis(this), regpressure_analysis(this),
+ performance_analysis(this),
dispatch_width(dispatch_width),
shader_time_index(shader_time_index),
bld(fs_builder(this, dispatch_width).at_end())
int shader_time_index)
: backend_shader(compiler, log_data, mem_ctx, shader,
&prog_data->base.base),
- key(&c->key), gs_compile(c),
- prog_data(&prog_data->base.base), prog(NULL),
+ key(&c->key.base), gs_compile(c),
+ prog_data(&prog_data->base.base),
+ live_analysis(this), regpressure_analysis(this),
+ performance_analysis(this),
dispatch_width(8),
shader_time_index(shader_time_index),
bld(fs_builder(this, dispatch_width).at_end())
void
fs_visitor::init()
{
- switch (stage) {
- case MESA_SHADER_FRAGMENT:
- key_tex = &((const brw_wm_prog_key *) key)->tex;
- break;
- case MESA_SHADER_VERTEX:
- key_tex = &((const brw_vs_prog_key *) key)->tex;
- break;
- case MESA_SHADER_TESS_CTRL:
- key_tex = &((const brw_tcs_prog_key *) key)->tex;
- break;
- case MESA_SHADER_TESS_EVAL:
- key_tex = &((const brw_tes_prog_key *) key)->tex;
- break;
- case MESA_SHADER_GEOMETRY:
- key_tex = &((const brw_gs_prog_key *) key)->tex;
- break;
- case MESA_SHADER_COMPUTE:
- key_tex = &((const brw_cs_prog_key*) key)->tex;
- break;
- default:
- unreachable("unhandled shader stage");
- }
+ if (key)
+ this->key_tex = &key->tex;
+ else
+ this->key_tex = NULL;
this->max_dispatch_width = 32;
this->prog_data = this->stage_prog_data;
this->first_non_payload_grf = 0;
this->max_grf = devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
- this->virtual_grf_start = NULL;
- this->virtual_grf_end = NULL;
- this->live_intervals = NULL;
- this->regs_live_at_ip = NULL;
-
this->uniforms = 0;
this->last_scratch = 0;
this->pull_constant_loc = NULL;
this->push_constant_loc = NULL;
- this->promoted_constants = 0,
+ this->shader_stats.scheduler_mode = NULL;
+ this->shader_stats.promoted_constants = 0,
+ this->grf_used = 0;
this->spilled_any_registers = false;
}
projects / mesa.git / blobdiff