intel/nir: Pass the nir_builder by reference in lower_alpha_to_coverage

[mesa.git] / src / intel / compiler / brw_fs_visitor.cpp

diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp
index 0d8b0f78a32a801f2acdb38aee7a5dc1e6f1c0f5..d8918858a8d6383c0beff67865f2a416133ace4c 100644 (file)
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -242,6 +242,9 @@ brw_rnd_mode_from_nir(unsigned mode, unsigned *mask)
    if (mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE)
       *mask |= BRW_CR0_FP_MODE_MASK;
 
+   if (*mask != 0)
+      assert((*mask & brw_mode) == brw_mode);
+
    return brw_mode;
 }
 
@@ -253,8 +256,11 @@ fs_visitor::emit_shader_float_controls_execution_mode()
       return;
 
    fs_builder abld = bld.annotate("shader floats control execution mode");
-   unsigned mask = 0;
-   unsigned mode = brw_rnd_mode_from_nir(execution_mode, &mask);
+   unsigned mask, mode = brw_rnd_mode_from_nir(execution_mode, &mask);
+
+   if (mask == 0)
+      return;
+
    abld.emit(SHADER_OPCODE_FLOAT_CONTROL_MODE, bld.null_reg_ud(),
              brw_imm_d(mode), brw_imm_d(mask));
 }
@@ -548,9 +554,13 @@ fs_visitor::emit_fb_writes()
        * XXX - Emit an extra single-source NULL RT-write marked LastRT in
        *       order to release the thread dependency without disabling
        *       SIMD32.
+       *
+       * The dual-source RT write messages may lead to hangs with SIMD16
+       * dispatch on ICL due some unknown reasons, see
+       * https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183
        */
-      limit_dispatch_width(16, "Dual source blending unsupported "
-                           "in SIMD32 mode.\n");
+      limit_dispatch_width(8, "Dual source blending unsupported "
+                           "in SIMD16 and SIMD32 modes.\n");
    }
 }
 
@@ -835,7 +845,7 @@ fs_visitor::emit_cs_terminate()
    assert(devinfo->gen >= 7);
 
    /* We are getting the thread ID from the compute shader header */
-   assert(stage == MESA_SHADER_COMPUTE);
+   assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL);
 
    /* We can't directly send from g0, since sends with EOT have to use
     * g112-127. So, copy it to a virtual register, The register allocator will
@@ -870,7 +880,7 @@ fs_visitor::emit_barrier()
    }
 
    /* We are getting the barrier ID from the compute shader header */
-   assert(stage == MESA_SHADER_COMPUTE);
+   assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL);
 
    fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
 
@@ -900,6 +910,7 @@ fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
      key(key), gs_compile(NULL), prog_data(prog_data),
      input_vue_map(input_vue_map),
      live_analysis(this), regpressure_analysis(this),
+     performance_analysis(this),
      dispatch_width(dispatch_width),
      shader_time_index(shader_time_index),
      bld(fs_builder(this, dispatch_width).at_end())
@@ -918,6 +929,7 @@ fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
      key(&c->key.base), gs_compile(c),
      prog_data(&prog_data->base.base),
      live_analysis(this), regpressure_analysis(this),
+     performance_analysis(this),
      dispatch_width(8),
      shader_time_index(shader_time_index),
      bld(fs_builder(this, dispatch_width).at_end())