intel/compiler: Allow MESA_SHADER_KERNEL

[mesa.git] / src / intel / compiler / brw_fs_visitor.cpp

diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp
index 5e06f10a0f40942297e4d9db558c7934b3ed193f..d8918858a8d6383c0beff67865f2a416133ace4c 100644 (file)
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -845,7 +845,7 @@ fs_visitor::emit_cs_terminate()
    assert(devinfo->gen >= 7);
 
    /* We are getting the thread ID from the compute shader header */
-   assert(stage == MESA_SHADER_COMPUTE);
+   assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL);
 
    /* We can't directly send from g0, since sends with EOT have to use
     * g112-127. So, copy it to a virtual register, The register allocator will
@@ -880,7 +880,7 @@ fs_visitor::emit_barrier()
    }
 
    /* We are getting the barrier ID from the compute shader header */
-   assert(stage == MESA_SHADER_COMPUTE);
+   assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL);
 
    fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);