intel/nir: Pass the nir_builder by reference in lower_alpha_to_coverage

[mesa.git] / src / intel / compiler / brw_fs_visitor.cpp

diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp
index e276227f0acf9b5b5b13e25d99f916b912239cb6..d8918858a8d6383c0beff67865f2a416133ace4c 100644 (file)
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -179,10 +179,10 @@ fs_visitor::emit_interpolation_setup_gen4()
 
    if (devinfo->has_pln) {
       for (unsigned i = 0; i < dispatch_width / 8; i++) {
-         abld.half(i).ADD(half(offset(delta_xy, abld, 0), i),
-                          half(this->pixel_x, i), xstart);
-         abld.half(i).ADD(half(offset(delta_xy, abld, 1), i),
-                          half(this->pixel_y, i), ystart);
+         abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 0), i),
+                             quarter(this->pixel_x, i), xstart);
+         abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 1), i),
+                             quarter(this->pixel_y, i), ystart);
       }
    } else {
       abld.ADD(offset(delta_xy, abld, 0), this->pixel_x, xstart);
@@ -242,6 +242,9 @@ brw_rnd_mode_from_nir(unsigned mode, unsigned *mask)
    if (mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE)
       *mask |= BRW_CR0_FP_MODE_MASK;
 
+   if (*mask != 0)
+      assert((*mask & brw_mode) == brw_mode);
+
    return brw_mode;
 }
 
@@ -253,8 +256,11 @@ fs_visitor::emit_shader_float_controls_execution_mode()
       return;
 
    fs_builder abld = bld.annotate("shader floats control execution mode");
-   unsigned mask = 0;
-   unsigned mode = brw_rnd_mode_from_nir(execution_mode, &mask);
+   unsigned mask, mode = brw_rnd_mode_from_nir(execution_mode, &mask);
+
+   if (mask == 0)
+      return;
+
    abld.emit(SHADER_OPCODE_FLOAT_CONTROL_MODE, bld.null_reg_ud(),
              brw_imm_d(mode), brw_imm_d(mask));
 }
@@ -360,9 +366,10 @@ fs_visitor::emit_interpolation_setup_gen6()
          for (unsigned c = 0; c < 2; c++) {
             for (unsigned q = 0; q < dispatch_width / 8; q++) {
                set_predicate(BRW_PREDICATE_NORMAL,
-                  bld.half(q).SEL(half(offset(delta_xy[i], bld, c), q),
-                                  half(offset(centroid_delta_xy, bld, c), q),
-                                  half(offset(pixel_delta_xy, bld, c), q)));
+                  bld.quarter(q).SEL(
+                     quarter(offset(delta_xy[i], bld, c), q),
+                     quarter(offset(centroid_delta_xy, bld, c), q),
+                     quarter(offset(pixel_delta_xy, bld, c), q)));
             }
          }
       }
@@ -539,16 +546,21 @@ fs_visitor::emit_fb_writes()
    inst->last_rt = true;
    inst->eot = true;
 
-   if (devinfo->gen == 11 && prog_data->dual_src_blend) {
+   if (devinfo->gen >= 11 && devinfo->gen <= 12 &&
+       prog_data->dual_src_blend) {
       /* The dual-source RT write messages fail to release the thread
-       * dependency on ICL with SIMD32 dispatch, leading to hangs.
+       * dependency on ICL and TGL with SIMD32 dispatch, leading to hangs.
        *
        * XXX - Emit an extra single-source NULL RT-write marked LastRT in
        *       order to release the thread dependency without disabling
        *       SIMD32.
+       *
+       * The dual-source RT write messages may lead to hangs with SIMD16
+       * dispatch on ICL due some unknown reasons, see
+       * https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183
        */
-      limit_dispatch_width(16, "Dual source blending unsupported "
-                           "in SIMD32 mode.\n");
+      limit_dispatch_width(8, "Dual source blending unsupported "
+                           "in SIMD16 and SIMD32 modes.\n");
    }
 }
 
@@ -698,8 +710,18 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
                sources[length++] = reg;
             }
          } else {
-            for (unsigned i = 0; i < 4; i++)
-               sources[length++] = offset(this->outputs[varying], bld, i);
+            int slot_offset = 0;
+
+            /* When using Primitive Replication, there may be multiple slots
+             * assigned to POS.
+             */
+            if (varying == VARYING_SLOT_POS)
+               slot_offset = slot - vue_map->varying_to_slot[VARYING_SLOT_POS];
+
+            for (unsigned i = 0; i < 4; i++) {
+               sources[length++] = offset(this->outputs[varying], bld,
+                                          i + (slot_offset * 4));
+            }
          }
          break;
       }
@@ -823,7 +845,7 @@ fs_visitor::emit_cs_terminate()
    assert(devinfo->gen >= 7);
 
    /* We are getting the thread ID from the compute shader header */
-   assert(stage == MESA_SHADER_COMPUTE);
+   assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL);
 
    /* We can't directly send from g0, since sends with EOT have to use
     * g112-127. So, copy it to a virtual register, The register allocator will
@@ -858,7 +880,7 @@ fs_visitor::emit_barrier()
    }
 
    /* We are getting the barrier ID from the compute shader header */
-   assert(stage == MESA_SHADER_COMPUTE);
+   assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL);
 
    fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
 
@@ -888,6 +910,7 @@ fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
      key(key), gs_compile(NULL), prog_data(prog_data),
      input_vue_map(input_vue_map),
      live_analysis(this), regpressure_analysis(this),
+     performance_analysis(this),
      dispatch_width(dispatch_width),
      shader_time_index(shader_time_index),
      bld(fs_builder(this, dispatch_width).at_end())
@@ -906,6 +929,7 @@ fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
      key(&c->key.base), gs_compile(c),
      prog_data(&prog_data->base.base),
      live_analysis(this), regpressure_analysis(this),
+     performance_analysis(this),
      dispatch_width(8),
      shader_time_index(shader_time_index),
      bld(fs_builder(this, dispatch_width).at_end())