anv: add new gem/drm helpers

[mesa.git] / src / intel / compiler / brw_vec4.h

diff --git a/src/intel/compiler/brw_vec4.h b/src/intel/compiler/brw_vec4.h
index 39ce51c7dcf2eb699ee997f6bd4fbe43df8c3cc7..73c18b6748c04b2d88f3928ca8d280c3f9f662f2 100644 (file)
--- a/src/intel/compiler/brw_vec4.h
+++ b/src/intel/compiler/brw_vec4.h
@@ -28,7 +28,9 @@
 
 #ifdef __cplusplus
 #include "brw_ir_vec4.h"
+#include "brw_ir_performance.h"
 #include "brw_vec4_builder.h"
+#include "brw_vec4_live_variables.h"
 #endif
 
 #include "compiler/glsl/ir.h"
@@ -45,15 +47,14 @@ brw_vec4_generate_assembly(const struct brw_compiler *compiler,
                            void *mem_ctx,
                            const nir_shader *nir,
                            struct brw_vue_prog_data *prog_data,
-                           const struct cfg_t *cfg);
+                           const struct cfg_t *cfg,
+                           const brw::performance &perf,
+                           struct brw_compile_stats *stats);
 
 #ifdef __cplusplus
 } /* extern "C" */
 
 namespace brw {
-
-class vec4_live_variables;
-
 /**
  * The vertex shader front-end.
  *
@@ -106,10 +107,10 @@ public:
 
    int first_non_payload_grf;
    unsigned int max_grf;
-   int *virtual_grf_start;
-   int *virtual_grf_end;
-   brw::vec4_live_variables *live_intervals;
-   dst_reg userplane[MAX_CLIP_PLANES];
+   BRW_ANALYSIS(live_analysis, brw::vec4_live_variables,
+                backend_shader *) live_analysis;
+   BRW_ANALYSIS(performance_analysis, brw::performance,
+                vec4_visitor *) performance_analysis;
 
    bool need_all_constants_in_pull_buffer;
 
@@ -132,24 +133,20 @@ public:
    bool reg_allocate();
    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
    int choose_spill_reg(struct ra_graph *g);
-   void spill_reg(int spill_reg);
+   void spill_reg(unsigned spill_reg);
    void move_grf_array_access_to_scratch();
    void move_uniform_array_access_to_pull_constants();
    void move_push_constants_to_pull_constants();
    void split_uniform_registers();
    void pack_uniform_registers();
-   void calculate_live_intervals();
-   void invalidate_live_intervals();
+   virtual void invalidate_analysis(brw::analysis_dependency_class c);
    void split_virtual_grfs();
    bool opt_vector_float();
    bool opt_reduce_swizzle();
    bool dead_code_eliminate();
-   int var_range_start(unsigned v, unsigned n) const;
-   int var_range_end(unsigned v, unsigned n) const;
-   bool virtual_grf_interferes(int a, int b);
    bool opt_cmod_propagation();
    bool opt_copy_propagation(bool do_constant_prop = true);
-   bool opt_cse_local(bblock_t *block);
+   bool opt_cse_local(bblock_t *block, const vec4_live_variables &live);
    bool opt_cse();
    bool opt_algebraic();
    bool opt_register_coalesce();
@@ -158,6 +155,7 @@ public:
    void opt_set_dependency_control();
    void opt_schedule_instructions();
    void convert_to_hw_regs();
+   void fixup_3src_null_dest();
 
    bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg);
    bool lower_simd_width();
@@ -230,20 +228,18 @@ public:
 #undef EMIT2
 #undef EMIT3
 
-   int implied_mrf_writes(vec4_instruction *inst);
-
    vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
                                  src_reg src0, src_reg src1);
 
-   vec4_instruction *emit_lrp(const dst_reg &dst, const src_reg &x,
-                              const src_reg &y, const src_reg &a);
-
    /**
     * Copy any live channel from \p src to the first channel of the
     * result.
     */
    src_reg emit_uniformize(const src_reg &src);
 
+   /** Fix all float operands of a 3-source instruction. */
+   void fix_float_operands(src_reg op[3], nir_alu_instr *instr);
+
    src_reg fix_3src_operand(const src_reg &src);
    src_reg resolve_source_modifiers(const src_reg &src);
 
@@ -313,15 +309,15 @@ public:
 
    src_reg get_timestamp();
 
-   void dump_instruction(backend_instruction *inst);
-   void dump_instruction(backend_instruction *inst, FILE *file);
+   void dump_instruction(const backend_instruction *inst) const;
+   void dump_instruction(const backend_instruction *inst, FILE *file) const;
 
    bool is_high_sampler(src_reg sampler);
 
    bool optimize_predicate(nir_alu_instr *instr, enum brw_predicate *predicate);
 
-   void emit_conversion_from_double(dst_reg dst, src_reg src, bool saturate);
-   void emit_conversion_to_double(dst_reg dst, src_reg src, bool saturate);
+   void emit_conversion_from_double(dst_reg dst, src_reg src);
+   void emit_conversion_to_double(dst_reg dst, src_reg src);
 
    vec4_instruction *shuffle_64bit_data(dst_reg dst, src_reg src,
                                         bool for_write,
@@ -337,6 +333,7 @@ public:
    virtual void nir_emit_block(nir_block *block);
    virtual void nir_emit_instr(nir_instr *instr);
    virtual void nir_emit_load_const(nir_load_const_instr *instr);
+   src_reg get_nir_ssbo_intrinsic_index(nir_intrinsic_instr *instr);
    virtual void nir_emit_intrinsic(nir_intrinsic_instr *instr);
    virtual void nir_emit_alu(nir_alu_instr *instr);
    virtual void nir_emit_jump(nir_jump_instr *instr);
@@ -353,6 +350,7 @@ public:
                        unsigned num_components = 4);
    src_reg get_nir_src(const nir_src &src,
                        unsigned num_components = 4);
+   src_reg get_nir_src_imm(const nir_src &src);
    src_reg get_indirect_offset(nir_intrinsic_instr *instr);
 
    dst_reg *nir_locals;