break;
}
+ case nir_intrinsic_memory_barrier_tcs_patch:
+ break;
+
default:
vec4_visitor::nir_emit_intrinsic(instr);
}
struct brw_tcs_prog_data *prog_data,
nir_shader *nir,
int shader_time_index,
+ struct brw_compile_stats *stats,
char **error_str)
{
const struct gen_device_info *devinfo = compiler->devinfo;
nir->info.system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID);
if (compiler->use_tcs_8_patch &&
- nir->info.tess.tcs_vertices_out <= 16 &&
+ nir->info.tess.tcs_vertices_out <= (devinfo->gen >= 12 ? 32 : 16) &&
2 + has_primitive_id + key->input_vertices <= 31) {
- /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First,
- * the "Instance" field limits the number of output vertices to [1, 16].
- * Secondly, the "Dispatch GRF Start Register for URB Data" field is
- * limited to [0, 31] - which imposes a limit on the input vertices.
+ /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, the
+ * "Instance" field limits the number of output vertices to [1, 16] on
+ * gen11 and below, or [1, 32] on gen12 and above. Secondly, the
+ * "Dispatch GRF Start Register for URB Data" field is limited to [0,
+ * 31] - which imposes a limit on the input vertices.
*/
vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_8_PATCH;
prog_data->instances = nir->info.tess.tcs_vertices_out;
if (is_scalar) {
fs_visitor v(compiler, log_data, mem_ctx, &key->base,
- &prog_data->base.base, NULL, nir, 8,
+ &prog_data->base.base, nir, 8,
shader_time_index, &input_vue_map);
if (!v.run_tcs()) {
if (error_str)
nir->info.name));
}
- g.generate_code(v.cfg, 8);
+ g.generate_code(v.cfg, 8, stats);
assembly = g.get_assembly();
} else {
assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
- &prog_data->base, v.cfg);
+ &prog_data->base, v.cfg, stats);
}
return assembly;