<struct name="HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD" length="4">
<field name="Indirect Payload Data Size in bits" start="0" end="31" type="uint"/>
<field name="Indirect Payload Base Address" start="32" end="95" type="address"/>
- <field name="Indirect Payload Base Address2" start="96" end="128" type="MEMORYADDRESSATTRIBUTES"/>
+ <field name="Indirect Payload Base Address2" start="96" end="127" type="MEMORYADDRESSATTRIBUTES"/>
</struct>
<struct name="HCP_REF_LIST_ENTRY" length="1">
<field name="Surface QPitch" start="32" end="46" type="uint"/>
<field name="Base Mip Level" start="51" end="55" type="u4.1"/>
<field name="MOCS" start="56" end="62" type="uint"/>
+ <field name="Enable Unorm Path In Color Pipe" start="63" end="63" type="bool"/>
<field name="Width" start="64" end="77" type="uint"/>
<field name="Height" start="80" end="93" type="uint"/>
<field name="Surface Pitch" start="96" end="113" type="uint"/>
<value name="180DEG" value="2"/>
<value name="270DEG" value="3"/>
</field>
- <field name="Force Non-Comparison Reduction Type" start="159" end="159" type="bool"/>
<field name="MIP Count / LOD" start="160" end="163" type="uint"/>
<field name="Surface Min LOD" start="164" end="167" type="uint"/>
<field name="Mip Tail Start LOD" start="168" end="171" type="uint"/>
<field name="Component Override W" start="15" end="15" type="bool"/>
</struct>
+ <struct name="SLICE_HASH_TABLE" length="32">
+ <group count="16" start="0" size="64">
+ <group count="16" start="0" size="4">
+ <field name="Entry" start="0" end="3" type="uint"/>
+ </group>
+ </group>
+ </struct>
+
<struct name="SO_DECL" length="1">
<field name="Component Mask" start="0" end="3" type="uint" default="0"/>
<field name="Register Index" start="4" end="9" type="uint"/>
- <field name="Hole Flag" start="11" end="11" type="uint"/>
+ <field name="Hole Flag" start="11" end="11" type="bool"/>
<field name="Output Buffer Slot" start="12" end="13" type="uint"/>
</struct>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
- <field name="Mask Bits" start="48" end="63" type="uint"/>
+ <field name="Cross Slice Hashing Mode" start="32" end="33" type="uint">
+ <value name="Normal Mode" value="0"/>
+ <value name="Disable" value="1"/>
+ <value name="hashing 32x32" value="3"/>
+ </field>
+ <field name="Subslice Hashing Mode" start="34" end="35" type="uint">
+ <value name="hashing 8x8" value="0"/>
+ <value name="hashing 16x4" value="1"/>
+ <value name="hashing 8x4" value="2"/>
+ <value name="hashing 16x16" value="3"/>
+ </field>
+ <field name="Slice Hashing Table Enable" start="38" end="38" type="bool"/>
+ <field name="Mask" start="48" end="63" type="mbo"/>
</instruction>
<instruction name="3DSTATE_AA_LINE_PARAMETERS" bias="2" length="3" engine="render">
<field name="Last Pixel Enable" start="127" end="127" type="bool"/>
</instruction>
+ <instruction name="3DSTATE_SLICE_TABLE_STATE_POINTERS" bias="2" length="2">
+ <field name="DWord Length" start="0" end="7" type="uint" default="0"/>
+ <field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="32"/>
+ <field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
+ <field name="Command SubType" start="27" end="28" type="uint" default="3"/>
+ <field name="Command Type" start="29" end="31" type="uint" default="3"/>
+ <field name="Slice Hash State Pointer Valid" start="32" end="32" type="bool"/>
+ <field name="Slice Hash Table State Pointer" start="38" end="63" type="offset"/>
+ </instruction>
+
<instruction name="3DSTATE_SO_BUFFER" bias="2" length="8" engine="render">
<field name="DWord Length" start="0" end="7" type="uint" default="6"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="24"/>
<instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
<field name="DWord Length" start="0" end="7" type="uint" default="4"/>
+ <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
</register>
<register name="CACHE_MODE_0" length="1" num="0x7000">
- <field name="Null tile fix disable" start="0" end="0" type="bool"/>
+ <field name="Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp" start="0" end="0" type="bool"/>
<field name="Disable clock gating in the pixel backend" start="1" end="1" type="bool"/>
- <field name="Hierarchical Z RAW Stall Optimization Disable" start="2" end="2" type="bool"/>
+ <field name="Hierarchical Z Disable" start="3" end="3" type="bool"/>
<field name="RCC Eviction Policy" start="4" end="4" type="bool"/>
- <field name="STC PMA Optimization Enable" start="5" end="5" type="bool"/>
- <field name="Sampler L2 Request Arbitration" start="6" end="7" type="uint">
- <value name="Round Robin" value="0"/>
- <value name="Fetch are Highest Priority" value="1"/>
- <value name="Constants are Highest Priority" value="2"/>
- </field>
+ <field name="STC PMA Optimization Disable" start="5" end="5" type="bool"/>
+ <field name="STC Read-Hit Wonly Optimization Disable" start="6" end="6" type="bool"/>
+ <field name="Depth Related Cache Pipelined Flush Disable" start="8" end="8" type="bool"/>
<field name="Sampler L2 TLB Prefetch Enable" start="9" end="9" type="bool"/>
- <field name="Sampler Set Remapping for 3D Disable" start="11" end="11" type="bool"/>
+ <field name="RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters" start="10" end="10" type="bool"/>
<field name="MSAA Compression Plane Number Threshold for eLLC" start="12" end="14" type="uint"/>
- <field name="Sampler L2 Disable" start="15" end="15" type="bool"/>
- <field name="Null tile fix disable Mask" start="16" end="16" type="bool"/>
+ <field name="Disable Repacking for Compression" start="15" end="15" type="bool"/>
+ <field name="Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp Mask" start="16" end="16" type="bool"/>
<field name="Disable clock gating in the pixel backend Mask" start="17" end="17" type="bool"/>
- <field name="Hierarchical Z RAW Stall Optimization Disable Mask" start="18" end="18" type="bool"/>
+ <field name="Hierarchical Z Disable Mask" start="19" end="19" type="bool"/>
<field name="RCC Eviction Policy Mask" start="20" end="20" type="bool"/>
- <field name="STC PMA Optimization Enable Mask" start="21" end="21" type="bool"/>
- <field name="Sampler L2 Request Arbitration Mask" start="22" end="23" type="uint"/>
+ <field name="STC PMA Optimization Disable Mask" start="21" end="21" type="bool"/>
+ <field name="STC Read-Hit Wonly Optimization Disable Mask" start="22" end="22" type="bool"/>
+ <field name="Depth Related Cache Pipelined Flush Disable Mask" start="24" end="24" type="bool"/>
<field name="Sampler L2 TLB Prefetch Enable Mask" start="25" end="25" type="bool"/>
- <field name="Sampler Set Remapping for 3D Disable Mask" start="27" end="27" type="bool"/>
+ <field name="RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters Mask" start="26" end="26" type="bool"/>
<field name="MSAA Compression Plane Number Threshold for eLLC Mask" start="28" end="30" type="uint"/>
- <field name="Sampler L2 Disable Mask" start="31" end="31" type="bool"/>
+ <field name="Disable Repacking for Compression Mask" start="31" end="31" type="bool"/>
</register>
<register name="CACHE_MODE_1" length="1" num="0x7004">
<field name="PS Thread Panic Dispatch Mask" start="22" end="23" type="uint"/>
</register>
+ <register name="COMMON_SLICE_CHICKEN4" length="1" num="0x7300">
+ <field name="Enable Hardware Filtering in WM" start="5" end="5" type="bool"/>
+ <field name="Enable Hardware Filtering in WM Mask" start="21" end="21" type="bool"/>
+ </register>
+
<register name="CS_CHICKEN1" length="1" num="0x2580">
<field name="Replay Mode" start="0" end="0" type="uint">
<value name="Mid-cmdbuffer Preemption" value="0"/>
</register>
<register name="L3CNTLREG" length="1" num="0x7034">
- <field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
<field name="Error Detection Behavior Control" start="9" end="9" type="bool"/>
<field name="Use Full Ways" start="10" end="10" type="bool"/>
<field name="All Allocation" start="25" end="31" type="uint"/>
</register>
+ <register name="PERFCNT1" length="2" num="0x91b8">
+ <field name="Value" start="0" end="43" type="uint"/>
+ <field name="Event Selection" start="52" end="59" type="uint"/>
+ <field name="Counter Clear" start="60" end="60" type="bool"/>
+ <field name="Edge Detect" start="61" end="61" type="bool"/>
+ <field name="Overflow Enable" start="62" end="62" type="bool"/>
+ <field name="Counter Enable" start="63" end="63" type="bool"/>
+ </register>
+
+ <register name="PERFCNT2" length="2" num="0x91c0">
+ <field name="Value" start="0" end="43" type="uint"/>
+ <field name="Event Selection" start="52" end="59" type="uint"/>
+ <field name="Counter Clear" start="60" end="60" type="bool"/>
+ <field name="Edge Detect" start="61" end="61" type="bool"/>
+ <field name="Overflow Enable" start="62" end="62" type="bool"/>
+ <field name="Counter Enable" start="63" end="63" type="bool"/>
+ </register>
+
<register name="PS_INVOCATION_COUNT" length="2" num="0x2348">
<field name="PS Invocation Count Report" start="0" end="63" type="uint"/>
</register>
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
+ <register name="RPSTAT0" length="1" num="0xa01c">
+ <field name="Previous GT Frequency" start="0" end="8" type="uint"/>
+ <field name="Current GT Frequency" start="23" end="31" type="uint"/>
+ </register>
+
<register name="SAMPLER_INSTDONE" length="1" num="0xe160">
<field name="IME Done" start="0" end="0" type="bool"/>
<field name="PL0 Done" start="1" end="1" type="bool"/>
<field name="Write Offset" start="2" end="31" type="offset"/>
</register>
+ <register name="TCCNTLREG" length="1" num="0xb0a4">
+ <field name="URB Partial Write Merging Enable" start="0" end="0" type="bool"/>
+ <field name="Color/Z Partial Write Merging Enable" start="1" end="1" type="bool"/>
+ <field name="L3 Data Partial Write Merging Enable" start="2" end="2" type="bool"/>
+ <field name="TC Disable" start="3" end="3" type="bool"/>
+ </register>
+
<register name="VCS_INSTDONE" length="1" num="0x1206c">
<field name="Ring Enable" start="0" end="0" type="bool"/>
<field name="USB Done" start="1" end="1" type="bool"/>
projects / mesa.git / blobdiff