#include "c99_compat.h"
#include "util/macros.h"
+#include "util/format/u_format.h"
#ifdef __cplusplus
extern "C" {
ISL_FORMAT_B10G10R10A2_UNORM = 209,
ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
ISL_FORMAT_R11G11B10_FLOAT = 211,
+ ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM = 213,
ISL_FORMAT_R32_SINT = 214,
ISL_FORMAT_R32_UINT = 215,
ISL_FORMAT_R32_FLOAT = 216,
ISL_FORMAT_GEN9_CCS_32BPP,
ISL_FORMAT_GEN9_CCS_64BPP,
ISL_FORMAT_GEN9_CCS_128BPP,
+ ISL_FORMAT_GEN12_CCS_8BPP_Y0,
+ ISL_FORMAT_GEN12_CCS_16BPP_Y0,
+ ISL_FORMAT_GEN12_CCS_32BPP_Y0,
+ ISL_FORMAT_GEN12_CCS_64BPP_Y0,
+ ISL_FORMAT_GEN12_CCS_128BPP_Y0,
+
+ /* An upper bound on the supported format enumerations */
+ ISL_NUM_FORMATS,
/* Hardware doesn't understand this out-of-band value */
ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
+ ISL_TILING_GEN12_CCS, /**< Tiling format for Gen12 CCS surfaces */
};
/**
#define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
#define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
#define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
+#define ISL_TILING_GEN12_CCS_BIT (1u << ISL_TILING_GEN12_CCS)
#define ISL_TILING_ANY_MASK (~0u)
#define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
* @invariant isl_surf::samples == 1
*/
ISL_AUX_USAGE_CCS_E,
+
+ /** The auxiliary surface provides full lossless color compression on
+ * Gen12.
+ *
+ * @invariant isl_surf::samples == 1
+ */
+ ISL_AUX_USAGE_GEN12_CCS_E,
+
+ /** The auxiliary surface provides full lossless media color compression
+ *
+ * @invariant isl_surf::samples == 1
+ */
+ ISL_AUX_USAGE_MC,
+
+ /** The auxiliary surface is a HiZ surface operating in write-through mode
+ * and CCS is also enabled
+ *
+ * In this mode, the HiZ and CCS surfaces act as a single fused compression
+ * surface where resolves and ambiguates operate on both surfaces at the
+ * same time. In this mode, the HiZ surface operates in write-through
+ * mode where it is only used for accelerating depth testing and not for
+ * actual compression. The CCS-compressed surface contains valid data at
+ * all times.
+ *
+ * @invariant isl_surf::samples == 1
+ */
+ ISL_AUX_USAGE_HIZ_CCS_WT,
+
+ /** The auxiliary surface is a HiZ surface with and CCS is also enabled
+ *
+ * In this mode, the HiZ and CCS surfaces act as a single fused compression
+ * surface where resolves and ambiguates operate on both surfaces at the
+ * same time. In this mode, full HiZ compression is enabled and the
+ * CCS-compressed main surface may not contain valid data. The only way to
+ * read the surface outside of the depth hardware is to do a full resolve
+ * which resolves both HiZ and CCS so the surface is in the pass-through
+ * state.
+ */
+ ISL_AUX_USAGE_HIZ_CCS,
+
+ /** The auxiliary surface is an MCS and CCS is also enabled
+ *
+ * In this mode, we have fused MCS+CCS compression where the MCS is used
+ * for fast-clears and "identical samples" compression just like on Gen7-11
+ * but each plane is then CCS compressed.
+ *
+ * @invariant isl_surf::samples > 1
+ */
+ ISL_AUX_USAGE_MCS_CCS,
+
+ /** CCS auxiliary data is used to compress a stencil buffer
+ *
+ * @invariant isl_surf::samples == 1
+ */
+ ISL_AUX_USAGE_STC_CCS,
};
/**
* the CCS and filling it with zeros.
*/
enum isl_aux_state {
- ISL_AUX_STATE_CLEAR = 0,
+#ifdef IN_UNIT_TEST
+ ISL_AUX_STATE_ASSERT,
+#endif
+ ISL_AUX_STATE_CLEAR,
ISL_AUX_STATE_PARTIAL_CLEAR,
ISL_AUX_STATE_COMPRESSED_CLEAR,
ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
* Enum which describes explicit aux transition operations.
*/
enum isl_aux_op {
+#ifdef IN_UNIT_TEST
+ ISL_AUX_OP_ASSERT,
+#endif
+
ISL_AUX_OP_NONE,
/** Fast Clear
/**
* @brief A channel select (also known as texture swizzle) value
*/
-enum isl_channel_select {
+enum PACKED isl_channel_select {
ISL_CHANNEL_SELECT_ZERO = 0,
ISL_CHANNEL_SELECT_ONE = 1,
ISL_CHANNEL_SELECT_RED = 4,
ISL_MSAA_LAYOUT_ARRAY,
};
+typedef enum {
+ ISL_MEMCPY = 0,
+ ISL_MEMCPY_BGRA8,
+ ISL_MEMCPY_STREAMING_LOAD,
+ ISL_MEMCPY_INVALID,
+} isl_memcpy_type;
struct isl_device {
const struct gen_device_info *info;
uint8_t stencil_offset;
uint8_t hiz_offset;
} ds;
+
+ struct {
+ uint32_t internal;
+ uint32_t external;
+ } mocs;
};
struct isl_extent2d {
struct isl_channel_layout {
enum isl_base_type type;
+ uint8_t start_bit; /**< Bit at which this channel starts */
uint8_t bits; /**< Size in bits */
};
* always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
* its physical size is 128B x 32rows, the same as a Y-tile.
*
- * @see isl_surf::row_pitch
+ * @see isl_surf::row_pitch_B
*/
struct isl_extent2d phys_extent_B;
};
uint32_t samples;
/** Lower bound for isl_surf::alignment, in bytes. */
- uint32_t min_alignment;
+ uint32_t min_alignment_B;
/**
* Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
* will fail if this is misaligned or out of bounds.
*/
- uint32_t row_pitch;
+ uint32_t row_pitch_B;
isl_surf_usage_flags_t usage;
/**
* Physical extent of the surface's base level, in units of physical
- * surface samples and aligned to the format's compression block.
+ * surface samples.
*
* Consider isl_dim_layout as an operator that transforms a logical surface
* layout to a physical surface layout. Then
uint32_t samples;
/** Total size of the surface, in bytes. */
- uint64_t size;
+ uint64_t size_B;
/** Required alignment for the surface's base address. */
- uint32_t alignment;
+ uint32_t alignment_B;
/**
* The interpretation of this field depends on the value of
* isl_tile_info::physical_extent_B. In particular, the width of the
- * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
+ * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
* and the distance in bytes between vertically adjacent tiles in the image
- * is given by row_pitch * isl_tile_info::physical_extent_B.height.
+ * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
*
* For linear images where isl_tile_info::physical_extent_B.height == 1,
* this cleanly reduces to being the distance, in bytes, between vertically
*
* @see isl_tile_info::phys_extent_B;
*/
- uint32_t row_pitch;
+ uint32_t row_pitch_B;
/**
* Pitch between physical array slices, in rows of surface elements.
/**
* The size of the buffer
*/
- uint64_t size;
+ uint64_t size_B;
/**
* The Memory Object Control state for the filled surface state.
*/
enum isl_format format;
- uint32_t stride;
+ /**
+ * The swizzle to use in the surface state
+ */
+ struct isl_swizzle swizzle;
+
+ uint32_t stride_B;
};
struct isl_depth_stencil_hiz_emit_info {
* The depth clear value
*/
float depth_clear_value;
+
+ /**
+ * Track stencil aux usage for Gen >= 12
+ */
+ enum isl_aux_usage stencil_aux_usage;
};
extern const struct isl_format_layout isl_format_layouts[];
static inline const struct isl_format_layout * ATTRIBUTE_CONST
isl_format_get_layout(enum isl_format fmt)
{
+ assert(fmt != ISL_FORMAT_UNSUPPORTED);
+ assert(fmt < ISL_NUM_FORMATS);
return &isl_format_layouts[fmt];
}
static inline const char * ATTRIBUTE_CONST
isl_format_get_name(enum isl_format fmt)
{
- return isl_format_layouts[fmt].name;
+ return isl_format_get_layout(fmt)->name;
}
+enum isl_format isl_format_for_pipe_format(enum pipe_format pf);
+
bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
enum isl_format format);
bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
bool isl_formats_are_ccs_e_compatible(const struct gen_device_info *devinfo,
enum isl_format format1,
enum isl_format format2);
+uint8_t isl_format_get_aux_map_encoding(enum isl_format format);
bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
isl_format_has_sint_channel(fmt);
}
+bool isl_format_has_color_component(enum isl_format fmt,
+ int component) ATTRIBUTE_CONST;
+
unsigned isl_format_get_num_channels(enum isl_format fmt);
uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
return false;
}
+static inline bool
+isl_format_is_planar(enum isl_format fmt)
+{
+ return fmt == ISL_FORMAT_PLANAR_420_8;
+}
+
static inline bool
isl_format_is_yuv(enum isl_format fmt)
{
static inline bool
isl_format_is_srgb(enum isl_format fmt)
{
- return isl_format_layouts[fmt].colorspace == ISL_COLORSPACE_SRGB;
+ return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
}
enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
{
if (isl_format_is_yuv(fmt))
return false;
- return isl_format_layouts[fmt].channels.r.bits > 0 &&
- isl_format_layouts[fmt].channels.g.bits > 0 &&
- isl_format_layouts[fmt].channels.b.bits > 0 &&
- isl_format_layouts[fmt].channels.a.bits == 0;
+
+ const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
+
+ return fmtl->channels.r.bits > 0 &&
+ fmtl->channels.g.bits > 0 &&
+ fmtl->channels.b.bits > 0 &&
+ fmtl->channels.a.bits == 0;
+}
+
+static inline bool
+isl_format_is_rgbx(enum isl_format fmt)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
+
+ return fmtl->channels.r.bits > 0 &&
+ fmtl->channels.g.bits > 0 &&
+ fmtl->channels.b.bits > 0 &&
+ fmtl->channels.a.bits > 0 &&
+ fmtl->channels.a.type == ISL_VOID;
}
enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
+enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
+
+union isl_color_value
+isl_color_value_swizzle_inv(union isl_color_value src,
+ struct isl_swizzle swizzle);
+
+void isl_color_value_pack(const union isl_color_value *value,
+ enum isl_format format,
+ uint32_t *data_out);
+void isl_color_value_unpack(union isl_color_value *value,
+ enum isl_format format,
+ const uint32_t *data_in);
bool isl_is_storage_image_format(enum isl_format fmt);
isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
enum isl_format fmt);
+static inline enum isl_tiling
+isl_tiling_flag_to_enum(isl_tiling_flags_t flag)
+{
+ assert(__builtin_popcount(flag) == 1);
+ return (enum isl_tiling) (__builtin_ffs(flag) - 1);
+}
+
static inline bool
isl_tiling_is_any_y(enum isl_tiling tiling)
{
enum isl_tiling
isl_tiling_from_i915_tiling(uint32_t tiling);
+/**
+ * Return an isl_aux_op needed to enable an access to occur in an
+ * isl_aux_state suitable for the isl_aux_usage.
+ *
+ * NOTE: If the access will invalidate the main surface, this function should
+ * not be called and the isl_aux_op of NONE should be used instead.
+ * Otherwise, an extra (but still lossless) ambiguate may occur.
+ *
+ * @invariant initial_state is possible with an isl_aux_usage compatible with
+ * the given usage. Two usages are compatible if it's possible to
+ * switch between them (e.g. CCS_E <-> CCS_D).
+ * @invariant fast_clear is false if the aux doesn't support fast clears.
+ */
+enum isl_aux_op
+isl_aux_prepare_access(enum isl_aux_state initial_state,
+ enum isl_aux_usage usage,
+ bool fast_clear_supported);
+
+/**
+ * Return the isl_aux_state entered after performing an isl_aux_op.
+ *
+ * @invariant initial_state is possible with the given usage.
+ * @invariant op is possible with the given usage.
+ * @invariant op must not cause HW to read from an invalid aux.
+ */
+enum isl_aux_state
+isl_aux_state_transition_aux_op(enum isl_aux_state initial_state,
+ enum isl_aux_usage usage,
+ enum isl_aux_op op);
+
+/**
+ * Return the isl_aux_state entered after performing a write.
+ *
+ * NOTE: full_surface should be true if the write covers the entire
+ * slice. Setting it to false in this case will still result in a
+ * correct (but imprecise) aux state.
+ *
+ * @invariant if usage is not ISL_AUX_USAGE_NONE, then initial_state is
+ * possible with the given usage.
+ * @invariant usage can be ISL_AUX_USAGE_NONE iff:
+ * * the main surface is valid, or
+ * * the main surface is being invalidated/replaced.
+ */
+enum isl_aux_state
+isl_aux_state_transition_write(enum isl_aux_state initial_state,
+ enum isl_aux_usage usage,
+ bool full_surface);
+
+bool
+isl_aux_usage_has_fast_clears(enum isl_aux_usage usage);
+
+static inline bool
+isl_aux_usage_has_hiz(enum isl_aux_usage usage)
+{
+ return usage == ISL_AUX_USAGE_HIZ ||
+ usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
+ usage == ISL_AUX_USAGE_HIZ_CCS;
+}
+
+static inline bool
+isl_aux_usage_has_mcs(enum isl_aux_usage usage)
+{
+ return usage == ISL_AUX_USAGE_MCS ||
+ usage == ISL_AUX_USAGE_MCS_CCS;
+}
+
+static inline bool
+isl_aux_usage_has_ccs(enum isl_aux_usage usage)
+{
+ return usage == ISL_AUX_USAGE_CCS_D ||
+ usage == ISL_AUX_USAGE_CCS_E ||
+ usage == ISL_AUX_USAGE_GEN12_CCS_E ||
+ usage == ISL_AUX_USAGE_MC ||
+ usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
+ usage == ISL_AUX_USAGE_HIZ_CCS ||
+ usage == ISL_AUX_USAGE_MCS_CCS ||
+ usage == ISL_AUX_USAGE_STC_CCS;
+}
+
+static inline bool
+isl_aux_state_has_valid_primary(enum isl_aux_state state)
+{
+ return state == ISL_AUX_STATE_RESOLVED ||
+ state == ISL_AUX_STATE_PASS_THROUGH ||
+ state == ISL_AUX_STATE_AUX_INVALID;
+}
+
+static inline bool
+isl_aux_state_has_valid_aux(enum isl_aux_state state)
+{
+ return state != ISL_AUX_STATE_AUX_INVALID;
+}
+
const struct isl_drm_modifier_info * ATTRIBUTE_CONST
isl_drm_modifier_get_info(uint64_t modifier);
if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE)
return ISL_AUX_STATE_AUX_INVALID;
- assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E);
return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
}
bool isl_color_value_is_zero_one(union isl_color_value value,
enum isl_format format);
+static inline bool
+isl_swizzle_is_identity(struct isl_swizzle swizzle)
+{
+ return swizzle.r == ISL_CHANNEL_SELECT_RED &&
+ swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
+ swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
+ swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
+}
+
+bool
+isl_swizzle_supports_rendering(const struct gen_device_info *devinfo,
+ struct isl_swizzle swizzle);
+
+struct isl_swizzle
+isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
+struct isl_swizzle
+isl_swizzle_invert(struct isl_swizzle swizzle);
+
#define isl_surf_init(dev, surf, ...) \
isl_surf_init_s((dev), (surf), \
&(struct isl_surf_init_info) { __VA_ARGS__ });
isl_surf_get_tile_info(const struct isl_surf *surf,
struct isl_tile_info *tile_info);
+bool
+isl_surf_supports_ccs(const struct isl_device *dev,
+ const struct isl_surf *surf);
+
bool
isl_surf_get_hiz_surf(const struct isl_device *dev,
const struct isl_surf *surf,
bool
isl_surf_get_ccs_surf(const struct isl_device *dev,
const struct isl_surf *surf,
- struct isl_surf *ccs_surf,
- uint32_t row_pitch /**< Ignored if 0 */);
+ struct isl_surf *aux_surf,
+ struct isl_surf *extra_aux_surf,
+ uint32_t row_pitch_B /**< Ignored if 0 */);
#define isl_surf_fill_state(dev, state, ...) \
isl_surf_fill_state_s((dev), (state), \
fmtl->bd * surf->image_alignment_el.d);
}
+/**
+ * Logical extent of level 0 in units of surface elements.
+ */
+static inline struct isl_extent4d
+isl_surf_get_logical_level0_el(const struct isl_surf *surf)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
+
+ return isl_extent4d(DIV_ROUND_UP(surf->logical_level0_px.w, fmtl->bw),
+ DIV_ROUND_UP(surf->logical_level0_px.h, fmtl->bh),
+ DIV_ROUND_UP(surf->logical_level0_px.d, fmtl->bd),
+ surf->logical_level0_px.a);
+}
+
+/**
+ * Physical extent of level 0 in units of surface elements.
+ */
+static inline struct isl_extent4d
+isl_surf_get_phys_level0_el(const struct isl_surf *surf)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
+
+ return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw),
+ DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh),
+ DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd),
+ surf->phys_level0_sa.a);
+}
+
/**
* Pitch between vertically adjacent surface elements, in bytes.
*/
static inline uint32_t
-isl_surf_get_row_pitch(const struct isl_surf *surf)
+isl_surf_get_row_pitch_B(const struct isl_surf *surf)
{
- return surf->row_pitch;
+ return surf->row_pitch_B;
}
/**
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
- assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
- return surf->row_pitch / (fmtl->bpb / 8);
+ assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
+ return surf->row_pitch_B / (fmtl->bpb / 8);
}
/**
static inline uint32_t
isl_surf_get_array_pitch(const struct isl_surf *surf)
{
- return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
+ return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
}
/**
uint32_t *x_offset_sa,
uint32_t *y_offset_sa);
+/**
+ * Calculate the range in bytes occupied by a subimage, to the nearest tile.
+ *
+ * The range returned will be the smallest memory range in which the give
+ * subimage fits, rounded to even tiles. Intel images do not usually have a
+ * direct subimage -> range mapping so the range returned may contain data
+ * from other sub-images. The returned range is a half-open interval where
+ * all of the addresses within the subimage are < end_tile_B.
+ *
+ * @invariant level < surface levels
+ * @invariant logical_array_layer < logical array length of surface
+ * @invariant logical_z_offset_px < logical depth of surface at level
+ */
+void
+isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
+ uint32_t level,
+ uint32_t logical_array_layer,
+ uint32_t logical_z_offset_px,
+ uint32_t *start_tile_B,
+ uint32_t *end_tile_B);
+
/**
* Create an isl_surf that represents a particular subimage in the surface.
*
void
isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
uint32_t bpb,
- uint32_t row_pitch,
+ uint32_t row_pitch_B,
uint32_t total_x_offset_el,
uint32_t total_y_offset_el,
uint32_t *base_address_offset,
static inline void
isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
enum isl_format format,
- uint32_t row_pitch,
+ uint32_t row_pitch_B,
uint32_t total_x_offset_sa,
uint32_t total_y_offset_sa,
uint32_t *base_address_offset,
const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
- isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch,
+ isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B,
total_x_offset, total_y_offset,
base_address_offset,
x_offset_sa, y_offset_sa);
isl_surf_get_depth_format(const struct isl_device *dev,
const struct isl_surf *surf);
+/**
+ * @brief performs a copy from linear to tiled surface
+ *
+ */
+void
+isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
+ uint32_t yt1, uint32_t yt2,
+ char *dst, const char *src,
+ uint32_t dst_pitch, int32_t src_pitch,
+ bool has_swizzling,
+ enum isl_tiling tiling,
+ isl_memcpy_type copy_type);
+
+/**
+ * @brief performs a copy from tiled to linear surface
+ *
+ */
+void
+isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
+ uint32_t yt1, uint32_t yt2,
+ char *dst, const char *src,
+ int32_t dst_pitch, uint32_t src_pitch,
+ bool has_swizzling,
+ enum isl_tiling tiling,
+ isl_memcpy_type copy_type);
+
#ifdef __cplusplus
}
#endif
projects / mesa.git / blobdiff