intel: Implement Gen12 workaround for array textures of size 1

[mesa.git] / src / intel / isl / isl_emit_depth_stencil.c

diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index c3815a6ac56e2aff6f626fa6e1728e1ad7426579..4906d95a49c51eaf168dff019b996e7b71d6f6ed 100644 (file)
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -146,6 +146,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
       sb.Depth = sb.RenderTargetViewExtent = info->view->array_len - 1;
       sb.SurfLOD = info->view->base_level;
       sb.MinimumArrayElement = info->view->base_array_layer;
+      sb.StencilCompressionEnable =
+         info->stencil_aux_usage == ISL_AUX_USAGE_CCS_E;
+      sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
 #elif GEN_GEN >= 8 || GEN_IS_HASWELL
       sb.StencilBufferEnable = true;
 #endif
@@ -192,6 +195,12 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
       hiz.SurfaceBaseAddress = info->hiz_address;
       hiz.MOCS = info->mocs;
       hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1;
+#if GEN_GEN >= 12
+      hiz.HierarchicalDepthBufferWriteThruEnable =
+         isl_surf_supports_hiz_ccs_wt(dev->info, info->depth_surf,
+                                      info->hiz_usage);
+#endif
+
 #if GEN_GEN >= 8
       /* From the SKL PRM Vol2a:
        *