anv: Properly cache brw_stage_prog_data::relocs

[mesa.git] / src / intel / isl / isl_gen4.c

diff --git a/src/intel/isl/isl_gen4.c b/src/intel/isl/isl_gen4.c
index 52aa5655bb2f78dab9cddb7628ebbad2735e4faf..a212d0ee0afdd7f65435735d8db2878a597eb718 100644 (file)
--- a/src/intel/isl/isl_gen4.c
+++ b/src/intel/isl/isl_gen4.c
@@ -25,10 +25,10 @@
 #include "isl_priv.h"
 
 bool
-gen4_choose_msaa_layout(const struct isl_device *dev,
-                        const struct isl_surf_init_info *info,
-                        enum isl_tiling tiling,
-                        enum isl_msaa_layout *msaa_layout)
+isl_gen4_choose_msaa_layout(const struct isl_device *dev,
+                            const struct isl_surf_init_info *info,
+                            enum isl_tiling tiling,
+                            enum isl_msaa_layout *msaa_layout)
 {
    /* Gen4 and Gen5 do not support MSAA */
    assert(info->samples >= 1);
@@ -38,11 +38,70 @@ gen4_choose_msaa_layout(const struct isl_device *dev,
 }
 
 void
-gen4_choose_image_alignment_el(const struct isl_device *dev,
-                               const struct isl_surf_init_info *restrict info,
-                               enum isl_tiling tiling,
-                               enum isl_msaa_layout msaa_layout,
-                               struct isl_extent3d *image_align_el)
+isl_gen4_filter_tiling(const struct isl_device *dev,
+                       const struct isl_surf_init_info *restrict info,
+                       isl_tiling_flags_t *flags)
+{
+   /* Gen4-5 only support linear, X, and Y-tiling. */
+   *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT | ISL_TILING_Y0_BIT);
+
+   if (isl_surf_usage_is_depth_or_stencil(info->usage)) {
+      assert(!ISL_DEV_USE_SEPARATE_STENCIL(dev));
+
+      /* From the g35 PRM Vol. 2, 3DSTATE_DEPTH_BUFFER::Tile Walk:
+       *
+       *    "The Depth Buffer, if tiled, must use Y-Major tiling"
+       *
+       *    Errata   Description    Project
+       *    BWT014   The Depth Buffer Must be Tiled, it cannot be linear. This
+       *    field must be set to 1 on DevBW-A.  [DevBW -A,B]
+       *
+       * In testing, the linear configuration doesn't seem to work on gen4.
+       */
+      *flags &= (ISL_DEV_GEN(dev) == 4 && !ISL_DEV_IS_G4X(dev)) ?
+                ISL_TILING_Y0_BIT : (ISL_TILING_Y0_BIT | ISL_TILING_LINEAR_BIT);
+   }
+
+   if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |
+                      ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT |
+                      ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) {
+      assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
+      isl_finishme("%s:%s: handle rotated display surfaces",
+                   __FILE__, __func__);
+   }
+
+   if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT |
+                      ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) {
+      assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
+      isl_finishme("%s:%s: handle flipped display surfaces",
+                   __FILE__, __func__);
+   }
+
+   if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
+      /* Before Skylake, the display engine does not accept Y */
+      *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
+   }
+
+   assert(info->samples == 1);
+
+   /* From the g35 PRM, Volume 1, 11.5.5, "Per-Stream Tile Format Support":
+    *
+    *    "NOTE: 128BPE Format Color buffer ( render target ) MUST be either
+    *    TileX or Linear."
+    *
+    * This is required all the way up to Sandy Bridge.
+    */
+   if (isl_format_get_layout(info->format)->bpb >= 128)
+      *flags &= ~ISL_TILING_Y0_BIT;
+}
+
+void
+isl_gen4_choose_image_alignment_el(const struct isl_device *dev,
+                                   const struct isl_surf_init_info *restrict info,
+                                   enum isl_tiling tiling,
+                                   enum isl_dim_layout dim_layout,
+                                   enum isl_msaa_layout msaa_layout,
+                                   struct isl_extent3d *image_align_el)
 {
    assert(info->samples == 1);
    assert(msaa_layout == ISL_MSAA_LAYOUT_NONE);