intel/tools: Simplify dstregion

[mesa.git] / src / intel / tools / i965_gram.y

diff --git a/src/intel/tools/i965_gram.y b/src/intel/tools/i965_gram.y
index a98451f15491340356cfc64dc43d2860c39a2e61..03ebc7e3e6da750ddf2ec9ebef8bf0983280279d 100644 (file)
--- a/src/intel/tools/i965_gram.y
+++ b/src/intel/tools/i965_gram.y
@@ -467,7 +467,7 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
 
 /* writemask */
 %type <integer> writemask_x writemask_y writemask_z writemask_w
-%type <reg> writemask
+%type <integer> writemask
 
 /* dst operand */
 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
@@ -481,7 +481,8 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
 %type <reg> indirectgenreg indirectregion
 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
-%type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
+%type <reg> region_wh directgenreg directmsgreg indirectmsgreg
+%type <integer> swizzle
 
 /* registers */
 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
@@ -1425,16 +1426,11 @@ dstoperand:
        dstreg dstregion writemask reg_type
        {
                $$ = $1;
-
-               if ($2 == -1) {
-                       $$.hstride = BRW_HORIZONTAL_STRIDE_1;
-                       $$.vstride = BRW_VERTICAL_STRIDE_1;
-                       $$.width = BRW_WIDTH_1;
-               } else {
-                       $$.hstride = $2;
-               }
+               $$.vstride = BRW_VERTICAL_STRIDE_1;
+               $$.width = BRW_WIDTH_1;
+               $$.hstride = $2;
                $$.type = $4;
-               $$.writemask = $3.writemask;
+               $$.writemask = $3;
                $$.swizzle = BRW_SWIZZLE_NOOP;
                $$.subnr = $$.subnr * brw_reg_type_to_size($4);
        }
@@ -1446,7 +1442,7 @@ dstoperandex:
                $$ = $1;
                $$.hstride = $2;
                $$.type = $4;
-               $$.writemask = $3.writemask;
+               $$.writemask = $3;
                $$.subnr = $$.subnr * brw_reg_type_to_size($4);
        }
        /* BSpec says "When the conditional modifier is present, updates
@@ -1456,14 +1452,10 @@ dstoperandex:
        | nullreg dstregion writemask reg_type
        {
                $$ = $1;
-               if ($2 == -1) {
-                       $$.hstride = BRW_HORIZONTAL_STRIDE_1;
-                       $$.vstride = BRW_VERTICAL_STRIDE_1;
-                       $$.width = BRW_WIDTH_1;
-               } else {
-                       $$.hstride = $2;
-               }
-               $$.writemask = $3.writemask;
+               $$.vstride = BRW_VERTICAL_STRIDE_1;
+               $$.width = BRW_WIDTH_1;
+               $$.hstride = $2;
+               $$.writemask = $3;
                $$.type = $4;
        }
        | threadcontrolreg
@@ -1518,28 +1510,23 @@ srcaccimm:
 immreg:
        immval imm_type
        {
-               uint32_t u32;
-               uint64_t u64;
                switch ($2) {
                case BRW_REGISTER_TYPE_UD:
-                       u32 = $1;
-                       $$ = brw_imm_ud(u32);
+                       $$ = brw_imm_ud($1);
                        break;
                case BRW_REGISTER_TYPE_D:
                        $$ = brw_imm_d($1);
                        break;
                case BRW_REGISTER_TYPE_UW:
-                       u32 = $1 | ($1 << 16);
-                       $$ = brw_imm_uw(u32);
+                       $$ = brw_imm_uw($1 | ($1 << 16));
                        break;
                case BRW_REGISTER_TYPE_W:
-                       u32 = $1;
-                       $$ = brw_imm_w(u32);
+                       $$ = brw_imm_w($1);
                        break;
                case BRW_REGISTER_TYPE_F:
                        $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
+                       /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
                        $$.u64 = $1;
-                       $$.ud = $1;
                        break;
                case BRW_REGISTER_TYPE_V:
                        $$ = brw_imm_v($1);
@@ -1548,16 +1535,13 @@ immreg:
                        $$ = brw_imm_uv($1);
                        break;
                case BRW_REGISTER_TYPE_VF:
-                       $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
-                       $$.d = $1;
+                       $$ = brw_imm_vf($1);
                        break;
                case BRW_REGISTER_TYPE_Q:
-                       u64 = $1;
-                       $$ = brw_imm_q(u64);
+                       $$ = brw_imm_q($1);
                        break;
                case BRW_REGISTER_TYPE_UQ:
-                       u64 = $1;
-                       $$ = brw_imm_uq(u64);
+                       $$ = brw_imm_uq($1);
                        break;
                case BRW_REGISTER_TYPE_DF:
                        $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
@@ -1658,7 +1642,7 @@ indirectsrcoperand:
                             $4.vstride,
                             $4.width,
                             $4.hstride,
-                            $5.swizzle,
+                            $5,
                             WRITEMASK_X);
 
                $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
@@ -1687,7 +1671,7 @@ directsrcoperand:
                             $4.vstride,
                             $4.width,
                             $4.hstride,
-                            $5.swizzle,
+                            $5,
                             WRITEMASK_X);
        }
        | srcarcoperandex
@@ -1933,7 +1917,10 @@ immval:
 
 /* Regions */
 dstregion:
-       %empty  { $$ = -1; }
+       %empty
+       {
+               $$ = BRW_HORIZONTAL_STRIDE_1;
+       }
        | LANGLE exp RANGLE
        {
                if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
@@ -2041,11 +2028,11 @@ imm_type:
 writemask:
        %empty
        {
-               $$= brw_set_writemask($$, WRITEMASK_XYZW);
+               $$ = WRITEMASK_XYZW;
        }
        | DOT writemask_x writemask_y writemask_z writemask_w
        {
-               $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
+               $$ = $2 | $3 | $4 | $5;
        }
        ;
 
@@ -2072,15 +2059,15 @@ writemask_w:
 swizzle:
        %empty
        {
-               $$.swizzle = BRW_SWIZZLE_NOOP;
+               $$ = BRW_SWIZZLE_NOOP;
        }
        | DOT chansel
        {
-               $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
+               $$ = BRW_SWIZZLE4($2, $2, $2, $2);
        }
        | DOT chansel chansel chansel chansel
        {
-               $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
+               $$ = BRW_SWIZZLE4($2, $3, $4, $5);
        }
        ;