/* dst operand */
%type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
-%type <reg> dstoperandex_ud_typed
%type <integer> dstregion
%type <integer> saturate relativelocation rellocation
/* src operand */
%type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
%type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
-%type <reg> srcarcoperandex_ud_typed srcimmtype indirectgenreg indirectregion
+%type <reg> srcimmtype indirectgenreg indirectregion
%type <reg> immreg src reg32 payload directgenreg_list addrparam region
%type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
| syncinstruction
| ternaryinstruction
| sendinstruction
+ | illegalinstruction
;
relocatableinstruction:
| loopinstruction
;
+illegalinstruction:
+ ILLEGAL execsize instoptions
+ {
+ brw_next_insn(p, $1);
+ brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
+ i965_asm_set_instruction_options(p, $3);
+ }
+ ;
+
/* Unary instruction */
unaryinstruction:
predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
$$.writemask = $3.writemask;
$$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
}
- | dstoperandex_ud_typed
- {
- $$ = $1;
- $$.hstride = 1;
- $$.type = BRW_REGISTER_TYPE_UD;
- }
/* BSpec says "When the conditional modifier is present, updates
* to the selected flag register also occur. In this case, the
* register region fields of the ‘null’ operand are valid."
}
;
-dstoperandex_ud_typed:
- controlreg
- | ipreg
- | channelenablereg
- | performancereg
- ;
-
dstoperandex_typed:
accreg
- | flagreg
| addrreg
+ | channelenablereg
+ | controlreg
+ | flagreg
+ | ipreg
| maskreg
+ | performancereg
| statereg
;
$$.d64 = $1;
break;
default:
- error(&@2, "Unkown immdediate type %s\n",
+ error(&@2, "Unknown immediate type %s\n",
brw_reg_type_to_letters($2.type));
}
}
BRW_SWIZZLE_NOOP,
WRITEMASK_XYZW);
}
- | srcarcoperandex_ud_typed
- {
- $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UD);
- }
| nullreg region srctype
{
$$ = set_direct_src_operand(&$1, $3.type);
}
;
-srcarcoperandex_ud_typed:
- controlreg
- | statereg
- | ipreg
- | channelenablereg
- ;
-
srcarcoperandex_typed:
- flagreg
+ channelenablereg
+ | controlreg
+ | flagreg
+ | ipreg
| maskreg
+ | statereg
;
indirectsrcoperand:
addrreg:
ADDRREG subregnum
{
- if ($1 != 0)
- error(&@1, "Address register number %d"
- "out of range\n", $1);
-
int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
if ($2 > subnr)
- error(&@2, "Address sub resgister number %d"
+ error(&@2, "Address sub register number %d"
"out of range\n", $2);
- $$ = brw_address_reg($2);
+ $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+ $$.nr = BRW_ARF_ADDRESS;
+ $$.subnr = $2;
}
;
error(&@2, "State sub register number %d"
" out of range\n", $2);
- $$ = brw_sr0_reg($2);
- $$.nr = $1;
+ $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+ $$.nr = BRW_ARF_STATE;
+ $$.subnr = $2;
}
;
controlreg:
CONTROLREG subregnum
{
- if ($1 > 0)
- error(&@1, "Control register number %d"
- " out of range\n", $1);
-
- if ($2 > 4)
+ if ($2 > 3)
error(&@2, "control sub register number %d"
" out of range\n", $2);
$$ = brw_cr0_reg($2);
- $$.nr = $1;
}
;
ipreg:
- IPREG srctype { $$ = brw_ip_reg(); }
+ IPREG { $$ = brw_ip_reg(); }
;
nullreg: