intel/tools: Simplify immediate handling

[mesa.git] / src / intel / tools / i965_gram.y

diff --git a/src/intel/tools/i965_gram.y b/src/intel/tools/i965_gram.y
index 89b3601135352dde31103bba6132e6f4b2ea5f8b..bddf9781ed9c5f64827357df9bfc2877ec64501b 100644 (file)
--- a/src/intel/tools/i965_gram.y
+++ b/src/intel/tools/i965_gram.y
@@ -467,7 +467,7 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
 
 /* writemask */
 %type <integer> writemask_x writemask_y writemask_z writemask_w
-%type <reg> writemask
+%type <integer> writemask
 
 /* dst operand */
 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
@@ -1435,7 +1435,7 @@ dstoperand:
                        $$.hstride = $2;
                }
                $$.type = $4;
-               $$.writemask = $3.writemask;
+               $$.writemask = $3;
                $$.swizzle = BRW_SWIZZLE_NOOP;
                $$.subnr = $$.subnr * brw_reg_type_to_size($4);
        }
@@ -1447,7 +1447,7 @@ dstoperandex:
                $$ = $1;
                $$.hstride = $2;
                $$.type = $4;
-               $$.writemask = $3.writemask;
+               $$.writemask = $3;
                $$.subnr = $$.subnr * brw_reg_type_to_size($4);
        }
        /* BSpec says "When the conditional modifier is present, updates
@@ -1464,7 +1464,7 @@ dstoperandex:
                } else {
                        $$.hstride = $2;
                }
-               $$.writemask = $3.writemask;
+               $$.writemask = $3;
                $$.type = $4;
        }
        | threadcontrolreg
@@ -1519,28 +1519,23 @@ srcaccimm:
 immreg:
        immval imm_type
        {
-               uint32_t u32;
-               uint64_t u64;
                switch ($2) {
                case BRW_REGISTER_TYPE_UD:
-                       u32 = $1;
-                       $$ = brw_imm_ud(u32);
+                       $$ = brw_imm_ud($1);
                        break;
                case BRW_REGISTER_TYPE_D:
                        $$ = brw_imm_d($1);
                        break;
                case BRW_REGISTER_TYPE_UW:
-                       u32 = $1 | ($1 << 16);
-                       $$ = brw_imm_uw(u32);
+                       $$ = brw_imm_uw($1 | ($1 << 16));
                        break;
                case BRW_REGISTER_TYPE_W:
-                       u32 = $1;
-                       $$ = brw_imm_w(u32);
+                       $$ = brw_imm_w($1);
                        break;
                case BRW_REGISTER_TYPE_F:
                        $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
+                       /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
                        $$.u64 = $1;
-                       $$.ud = $1;
                        break;
                case BRW_REGISTER_TYPE_V:
                        $$ = brw_imm_v($1);
@@ -1549,16 +1544,13 @@ immreg:
                        $$ = brw_imm_uv($1);
                        break;
                case BRW_REGISTER_TYPE_VF:
-                       $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
-                       $$.d = $1;
+                       $$ = brw_imm_vf($1);
                        break;
                case BRW_REGISTER_TYPE_Q:
-                       u64 = $1;
-                       $$ = brw_imm_q(u64);
+                       $$ = brw_imm_q($1);
                        break;
                case BRW_REGISTER_TYPE_UQ:
-                       u64 = $1;
-                       $$ = brw_imm_uq(u64);
+                       $$ = brw_imm_uq($1);
                        break;
                case BRW_REGISTER_TYPE_DF:
                        $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
@@ -2042,11 +2034,11 @@ imm_type:
 writemask:
        %empty
        {
-               $$= brw_set_writemask($$, WRITEMASK_XYZW);
+               $$ = WRITEMASK_XYZW;
        }
        | DOT writemask_x writemask_y writemask_z writemask_w
        {
-               $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
+               $$ = $2 | $3 | $4 | $5;
        }
        ;