case BRW_OPCODE_PLN:
brw_PLN(p, dest, src0, src1);
break;
+ case BRW_OPCODE_ROL:
+ brw_ROL(p, dest, src0, src1);
+ break;
+ case BRW_OPCODE_ROR:
+ brw_ROR(p, dest, src0, src1);
+ break;
case BRW_OPCODE_SAD2:
fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
break;
int integer;
unsigned long long int llint;
struct brw_reg reg;
+ enum brw_reg_type reg_type;
struct brw_codegen *program;
struct predicate predicate;
struct condition condition;
/* writemask */
%type <integer> writemask_x writemask_y writemask_z writemask_w
-%type <reg> writemask
+%type <integer> writemask
/* dst operand */
-%type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
-%type <reg> dstoperandex_ud_typed
+%type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
%type <integer> dstregion
%type <integer> saturate relativelocation rellocation
/* src operand */
%type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
-%type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
-%type <reg> srcarcoperandex_ud_typed srcimmtype indirectgenreg indirectregion
+%type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
+%type <reg> indirectgenreg indirectregion
%type <reg> immreg src reg32 payload directgenreg_list addrparam region
-%type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
+%type <reg> region_wh directgenreg directmsgreg indirectmsgreg
+%type <integer> swizzle
/* registers */
%type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
%type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
%type <integer> subregnum
+/* register types */
+%type <reg_type> reg_type imm_type
+
/* immediate values */
%type <llint> immval
| syncinstruction
| ternaryinstruction
| sendinstruction
+ | illegalinstruction
;
relocatableinstruction:
| loopinstruction
;
+illegalinstruction:
+ ILLEGAL execsize instoptions
+ {
+ brw_next_insn(p, $1);
+ brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
+ i965_asm_set_instruction_options(p, $3);
+ }
+ ;
+
/* Unary instruction */
unaryinstruction:
predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
| MACH
| MUL
| PLN
+ | ROL
+ | ROR
| SAD2
| SADA2
| SUBB
if (p->devinfo->gen >= 7)
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
$9.nib_ctrl);
-
}
;
if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
} else {
- brw_inst_set_send_ex_desc(p->devinfo, brw_last_inst, $8);
+ brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
}
brw_inst_set_bits(brw_last_inst, 127, 96, $7);
brw_set_src1(p, brw_last_inst, $6);
brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
- brw_inst_set_send_ex_desc(p->devinfo, brw_last_inst, $8);
+ brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
;
dstoperand:
- dstreg dstregion writemask dsttype
+ dstreg dstregion writemask reg_type
{
$$ = $1;
} else {
$$.hstride = $2;
}
- $$.type = $4.type;
- $$.writemask = $3.writemask;
+ $$.type = $4;
+ $$.writemask = $3;
$$.swizzle = BRW_SWIZZLE_NOOP;
- $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
+ $$.subnr = $$.subnr * brw_reg_type_to_size($4);
}
;
dstoperandex:
- dstoperandex_typed dstregion writemask dsttype
+ dstoperandex_typed dstregion writemask reg_type
{
$$ = $1;
$$.hstride = $2;
- $$.type = $4.type;
- $$.writemask = $3.writemask;
- $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
- }
- | dstoperandex_ud_typed
- {
- $$ = $1;
- $$.hstride = 1;
- $$.type = BRW_REGISTER_TYPE_UD;
+ $$.type = $4;
+ $$.writemask = $3;
+ $$.subnr = $$.subnr * brw_reg_type_to_size($4);
}
/* BSpec says "When the conditional modifier is present, updates
* to the selected flag register also occur. In this case, the
* register region fields of the ‘null’ operand are valid."
*/
- | nullreg dstregion writemask dsttype
+ | nullreg dstregion writemask reg_type
{
$$ = $1;
if ($2 == -1) {
} else {
$$.hstride = $2;
}
- $$.writemask = $3.writemask;
- $$.type = $4.type;
+ $$.writemask = $3;
+ $$.type = $4;
}
| threadcontrolreg
{
}
;
-dstoperandex_ud_typed:
- controlreg
- | ipreg
- | channelenablereg
- | performancereg
- ;
-
dstoperandex_typed:
accreg
- | flagreg
| addrreg
+ | channelenablereg
+ | controlreg
+ | flagreg
+ | ipreg
| maskreg
+ | performancereg
| statereg
;
;
immreg:
- immval srcimmtype
+ immval imm_type
{
- uint32_t u32;
- uint64_t u64;
- switch ($2.type) {
+ switch ($2) {
case BRW_REGISTER_TYPE_UD:
- u32 = $1;
- $$ = brw_imm_ud(u32);
+ $$ = brw_imm_ud($1);
break;
case BRW_REGISTER_TYPE_D:
$$ = brw_imm_d($1);
break;
case BRW_REGISTER_TYPE_UW:
- u32 = $1 | ($1 << 16);
- $$ = brw_imm_uw(u32);
+ $$ = brw_imm_uw($1 | ($1 << 16));
break;
case BRW_REGISTER_TYPE_W:
- u32 = $1;
- $$ = brw_imm_w(u32);
+ $$ = brw_imm_w($1);
break;
case BRW_REGISTER_TYPE_F:
$$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
+ /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
$$.u64 = $1;
- $$.ud = $1;
break;
case BRW_REGISTER_TYPE_V:
$$ = brw_imm_v($1);
$$ = brw_imm_uv($1);
break;
case BRW_REGISTER_TYPE_VF:
- $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
- $$.d = $1;
+ $$ = brw_imm_vf($1);
break;
case BRW_REGISTER_TYPE_Q:
- u64 = $1;
- $$ = brw_imm_q(u64);
+ $$ = brw_imm_q($1);
break;
case BRW_REGISTER_TYPE_UQ:
- u64 = $1;
- $$ = brw_imm_uq(u64);
+ $$ = brw_imm_uq($1);
break;
case BRW_REGISTER_TYPE_DF:
$$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
$$.d64 = $1;
break;
default:
- error(&@2, "Unkown immdediate type %s\n",
- brw_reg_type_to_letters($2.type));
+ error(&@2, "Unknown immediate type %s\n",
+ brw_reg_type_to_letters($2));
}
}
;
reg32:
- directgenreg region srctype
+ directgenreg region reg_type
{
- $$ = set_direct_src_operand(&$1, $3.type);
+ $$ = set_direct_src_operand(&$1, $3);
$$ = stride($$, $2.vstride, $2.width, $2.hstride);
}
;
directsrcaccoperand:
directsrcoperand
- | accreg region srctype
+ | accreg region reg_type
{
- $$ = set_direct_src_operand(&$1, $3.type);
+ $$ = set_direct_src_operand(&$1, $3);
$$.vstride = $2.vstride;
$$.width = $2.width;
$$.hstride = $2.hstride;
;
srcarcoperandex:
- srcarcoperandex_typed region srctype
+ srcarcoperandex_typed region reg_type
{
$$ = brw_reg($1.file,
$1.nr,
$1.subnr,
0,
0,
- $3.type,
+ $3,
$2.vstride,
$2.width,
$2.hstride,
BRW_SWIZZLE_NOOP,
WRITEMASK_XYZW);
}
- | srcarcoperandex_ud_typed
+ | nullreg region reg_type
{
- $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UD);
- }
- | nullreg region srctype
- {
- $$ = set_direct_src_operand(&$1, $3.type);
+ $$ = set_direct_src_operand(&$1, $3);
$$.vstride = $2.vstride;
$$.width = $2.width;
$$.hstride = $2.hstride;
}
;
-srcarcoperandex_ud_typed:
- controlreg
- | statereg
- | ipreg
- | channelenablereg
- ;
-
srcarcoperandex_typed:
- flagreg
+ channelenablereg
+ | controlreg
+ | flagreg
+ | ipreg
| maskreg
+ | statereg
;
indirectsrcoperand:
- negate abs indirectgenreg indirectregion swizzle srctype
+ negate abs indirectgenreg indirectregion swizzle reg_type
{
$$ = brw_reg($3.file,
0,
$3.subnr,
$1, // negate
$2, // abs
- $6.type,
+ $6,
$4.vstride,
$4.width,
$4.hstride,
- $5.swizzle,
+ $5,
WRITEMASK_X);
$$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
;
directsrcoperand:
- negate abs directgenreg_list region swizzle srctype
+ negate abs directgenreg_list region swizzle reg_type
{
$$ = brw_reg($3.file,
$3.nr,
$3.subnr,
$1,
$2,
- $6.type,
+ $6,
$4.vstride,
$4.width,
$4.hstride,
- $5.swizzle,
+ $5,
WRITEMASK_X);
}
| srcarcoperandex
addrreg:
ADDRREG subregnum
{
- if ($1 != 0)
- error(&@1, "Address register number %d"
- "out of range\n", $1);
-
int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
if ($2 > subnr)
- error(&@2, "Address sub resgister number %d"
+ error(&@2, "Address sub register number %d"
"out of range\n", $2);
- $$ = brw_address_reg($2);
+ $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+ $$.nr = BRW_ARF_ADDRESS;
+ $$.subnr = $2;
}
;
error(&@2, "State sub register number %d"
" out of range\n", $2);
- $$ = brw_sr0_reg($2);
- $$.nr = $1;
+ $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+ $$.nr = BRW_ARF_STATE;
+ $$.subnr = $2;
}
;
controlreg:
CONTROLREG subregnum
{
- if ($1 > 0)
- error(&@1, "Control register number %d"
- " out of range\n", $1);
-
- if ($2 > 4)
+ if ($2 > 3)
error(&@2, "control sub register number %d"
" out of range\n", $2);
$$ = brw_cr0_reg($2);
- $$.nr = $1;
}
;
ipreg:
- IPREG srctype { $$ = brw_ip_reg(); }
+ IPREG { $$ = brw_ip_reg(); }
;
nullreg:
}
;
-srctype:
- %empty { $$ = retype($$, BRW_REGISTER_TYPE_F); }
- | TYPE_F { $$ = retype($$, BRW_REGISTER_TYPE_F); }
- | TYPE_UD { $$ = retype($$, BRW_REGISTER_TYPE_UD); }
- | TYPE_D { $$ = retype($$, BRW_REGISTER_TYPE_D); }
- | TYPE_UW { $$ = retype($$, BRW_REGISTER_TYPE_UW); }
- | TYPE_W { $$ = retype($$, BRW_REGISTER_TYPE_W); }
- | TYPE_UB { $$ = retype($$, BRW_REGISTER_TYPE_UB); }
- | TYPE_B { $$ = retype($$, BRW_REGISTER_TYPE_B); }
- | TYPE_DF { $$ = retype($$, BRW_REGISTER_TYPE_DF); }
- | TYPE_UQ { $$ = retype($$, BRW_REGISTER_TYPE_UQ); }
- | TYPE_Q { $$ = retype($$, BRW_REGISTER_TYPE_Q); }
- | TYPE_HF { $$ = retype($$, BRW_REGISTER_TYPE_HF); }
- | TYPE_NF { $$ = retype($$, BRW_REGISTER_TYPE_NF); }
+reg_type:
+ TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
+ | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
+ | TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
+ | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
+ | TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
+ | TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
+ | TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
+ | TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; }
+ | TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; }
+ | TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; }
+ | TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; }
+ | TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; }
;
-srcimmtype:
- srctype { $$ = $1; }
- | TYPE_V { $$ = retype($$, BRW_REGISTER_TYPE_V); }
- | TYPE_VF { $$ = retype($$, BRW_REGISTER_TYPE_VF); }
- | TYPE_UV { $$ = retype($$, BRW_REGISTER_TYPE_UV); }
- ;
-
-dsttype:
- srctype { $$ = $1; }
+imm_type:
+ reg_type { $$ = $1; }
+ | TYPE_V { $$ = BRW_REGISTER_TYPE_V; }
+ | TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; }
+ | TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; }
;
writemask:
%empty
{
- $$= brw_set_writemask($$, WRITEMASK_XYZW);
+ $$ = WRITEMASK_XYZW;
}
| DOT writemask_x writemask_y writemask_z writemask_w
{
- $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
+ $$ = $2 | $3 | $4 | $5;
}
;
swizzle:
%empty
{
- $$.swizzle = BRW_SWIZZLE_NOOP;
+ $$ = BRW_SWIZZLE_NOOP;
}
| DOT chansel
{
- $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
+ $$ = BRW_SWIZZLE4($2, $2, $2, $2);
}
| DOT chansel chansel chansel chansel
{
- $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
+ $$ = BRW_SWIZZLE4($2, $3, $4, $5);
}
;
projects / mesa.git / blobdiff