}
static bool
-upload_blorp_shader(struct blorp_batch *batch,
+upload_blorp_shader(struct blorp_batch *batch, uint32_t stage,
const void *key, uint32_t key_size,
const void *kernel, uint32_t kernel_size,
const struct brw_stage_prog_data *prog_data,
};
struct anv_shader_bin *bin =
- anv_pipeline_cache_upload_kernel(&device->default_pipeline_cache,
+ anv_pipeline_cache_upload_kernel(&device->default_pipeline_cache, stage,
key, key_size, kernel, kernel_size,
- NULL, 0,
prog_data, prog_data_size,
NULL, 0, NULL, &bind_map);
anv_device_init_blorp(struct anv_device *device)
{
blorp_init(&device->blorp, device, &device->isl_dev);
- device->blorp.compiler = device->instance->physicalDevice.compiler;
+ device->blorp.compiler = device->physical->compiler;
device->blorp.lookup_shader = lookup_blorp_shader;
device->blorp.upload_shader = upload_blorp_shader;
switch (device->info.gen) {
get_blorp_surf_for_anv_image(const struct anv_device *device,
const struct anv_image *image,
VkImageAspectFlags aspect,
+ VkImageUsageFlags usage,
VkImageLayout layout,
enum isl_aux_usage aux_usage,
struct blorp_surf *blorp_surf)
{
uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
- if (layout != ANV_IMAGE_LAYOUT_EXPLICIT_AUX)
- aux_usage = anv_layout_to_aux_usage(&device->info, image, aspect, layout);
+ if (layout != ANV_IMAGE_LAYOUT_EXPLICIT_AUX) {
+ assert(usage != 0);
+ aux_usage = anv_layout_to_aux_usage(&device->info, image,
+ aspect, usage, layout);
+ }
const struct anv_surface *surface = &image->planes[plane].surface;
*blorp_surf = (struct blorp_surf) {
const struct anv_address clear_color_addr =
anv_image_get_clear_color_addr(device, image, aspect);
blorp_surf->clear_color_addr = anv_to_blorp_address(clear_color_addr);
- } else if (aspect & VK_IMAGE_ASPECT_DEPTH_BIT
- && device->info.gen >= 10) {
- /* Vulkan always clears to 1.0. On gen < 10, we set that directly in
- * the state packet. For gen >= 10, must provide the clear value in a
- * buffer. We have a single global buffer that stores the 1.0 value.
- */
- const struct anv_address clear_color_addr = (struct anv_address) {
- .bo = device->hiz_clear_bo,
- };
- blorp_surf->clear_color_addr = anv_to_blorp_address(clear_color_addr);
+ } else if (aspect & VK_IMAGE_ASPECT_DEPTH_BIT) {
+ if (device->info.gen >= 10) {
+ /* Vulkan always clears to 1.0. On gen < 10, we set that directly
+ * in the state packet. For gen >= 10, must provide the clear
+ * value in a buffer. We have a single global buffer that stores
+ * the 1.0 value.
+ */
+ const struct anv_address clear_color_addr = (struct anv_address) {
+ .bo = device->hiz_clear_bo,
+ };
+ blorp_surf->clear_color_addr =
+ anv_to_blorp_address(clear_color_addr);
+ } else {
+ blorp_surf->clear_color = (union isl_color_value) {
+ .f32 = { ANV_HZ_FC_VAL },
+ };
+ }
}
}
}
struct blorp_surf src_surf, dst_surf;
get_blorp_surf_for_anv_image(cmd_buffer->device,
src_image, 1UL << aspect_bit,
+ VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
srcImageLayout, ISL_AUX_USAGE_NONE,
&src_surf);
get_blorp_surf_for_anv_image(cmd_buffer->device,
dst_image, 1UL << aspect_bit,
+ VK_IMAGE_USAGE_TRANSFER_DST_BIT,
dstImageLayout, ISL_AUX_USAGE_NONE,
&dst_surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
} else {
struct blorp_surf src_surf, dst_surf;
get_blorp_surf_for_anv_image(cmd_buffer->device, src_image, src_mask,
+ VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
srcImageLayout, ISL_AUX_USAGE_NONE,
&src_surf);
get_blorp_surf_for_anv_image(cmd_buffer->device, dst_image, dst_mask,
+ VK_IMAGE_USAGE_TRANSFER_DST_BIT,
dstImageLayout, ISL_AUX_USAGE_NONE,
&dst_surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image, dst_mask,
blorp_batch_finish(&batch);
}
+static enum isl_format
+isl_format_for_size(unsigned size_B)
+{
+ /* Prefer 32-bit per component formats for CmdFillBuffer */
+ switch (size_B) {
+ case 1: return ISL_FORMAT_R8_UINT;
+ case 2: return ISL_FORMAT_R16_UINT;
+ case 3: return ISL_FORMAT_R8G8B8_UINT;
+ case 4: return ISL_FORMAT_R32_UINT;
+ case 6: return ISL_FORMAT_R16G16B16_UINT;
+ case 8: return ISL_FORMAT_R32G32_UINT;
+ case 12: return ISL_FORMAT_R32G32B32_UINT;
+ case 16: return ISL_FORMAT_R32G32B32A32_UINT;
+ default:
+ unreachable("Unknown format size");
+ }
+}
+
static void
copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
struct anv_buffer *anv_buffer,
const VkImageAspectFlags aspect = pRegions[r].imageSubresource.aspectMask;
get_blorp_surf_for_anv_image(cmd_buffer->device, anv_image, aspect,
+ buffer_to_image ?
+ VK_IMAGE_USAGE_TRANSFER_DST_BIT :
+ VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
image_layout, ISL_AUX_USAGE_NONE,
&image.surf);
image.offset =
anv_get_layerCount(anv_image, &pRegions[r].imageSubresource);
}
- const enum isl_format buffer_format =
+ const enum isl_format linear_format =
anv_get_isl_format(&cmd_buffer->device->info, anv_image->vk_format,
aspect, VK_IMAGE_TILING_LINEAR);
+ const struct isl_format_layout *linear_fmtl =
+ isl_format_get_layout(linear_format);
- const VkExtent3D bufferImageExtent = {
- .width = pRegions[r].bufferRowLength ?
- pRegions[r].bufferRowLength : extent.width,
- .height = pRegions[r].bufferImageHeight ?
- pRegions[r].bufferImageHeight : extent.height,
- };
+ const uint32_t buffer_row_length =
+ pRegions[r].bufferRowLength ?
+ pRegions[r].bufferRowLength : extent.width;
- const struct isl_format_layout *buffer_fmtl =
- isl_format_get_layout(buffer_format);
+ const uint32_t buffer_image_height =
+ pRegions[r].bufferImageHeight ?
+ pRegions[r].bufferImageHeight : extent.height;
const uint32_t buffer_row_pitch =
- DIV_ROUND_UP(bufferImageExtent.width, buffer_fmtl->bw) *
- (buffer_fmtl->bpb / 8);
+ DIV_ROUND_UP(buffer_row_length, linear_fmtl->bw) *
+ (linear_fmtl->bpb / 8);
const uint32_t buffer_layer_stride =
- DIV_ROUND_UP(bufferImageExtent.height, buffer_fmtl->bh) *
+ DIV_ROUND_UP(buffer_image_height, linear_fmtl->bh) *
buffer_row_pitch;
+ /* Some formats have additional restrictions which may cause ISL to
+ * fail to create a surface for us. Some examples include:
+ *
+ * 1. ASTC formats are not allowed to be LINEAR and must be tiled
+ * 2. YCbCr formats have to have 2-pixel aligned strides
+ *
+ * To avoid these issues, we always bind the buffer as if it's a
+ * "normal" format like RGBA32_UINT. Since we're using blorp_copy,
+ * the format doesn't matter as long as it has the right bpb.
+ */
+ const VkExtent2D buffer_extent = {
+ .width = DIV_ROUND_UP(extent.width, linear_fmtl->bw),
+ .height = DIV_ROUND_UP(extent.height, linear_fmtl->bh),
+ };
+ const enum isl_format buffer_format =
+ isl_format_for_size(linear_fmtl->bpb / 8);
+
struct isl_surf buffer_isl_surf;
get_blorp_surf_for_anv_buffer(cmd_buffer->device,
anv_buffer, pRegions[r].bufferOffset,
- extent.width, extent.height,
+ buffer_extent.width, buffer_extent.height,
buffer_row_pitch, buffer_format,
&buffer.surf, &buffer_isl_surf);
bool dst_has_shadow = false;
struct blorp_surf dst_shadow_surf;
if (&image == dst) {
+ /* In this case, the source is the buffer and, since blorp takes its
+ * copy dimensions in terms of the source format, we have to use the
+ * scaled down version for compressed textures because the source
+ * format is an RGB format.
+ */
+ extent.width = buffer_extent.width;
+ extent.height = buffer_extent.height;
+
anv_cmd_buffer_mark_image_written(cmd_buffer, anv_image,
aspect, dst->surf.aux_usage,
dst->level,
anv_foreach_image_aspect_bit(aspect_bit, src_image, src_res->aspectMask) {
get_blorp_surf_for_anv_image(cmd_buffer->device,
src_image, 1U << aspect_bit,
+ VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
srcImageLayout, ISL_AUX_USAGE_NONE, &src);
get_blorp_surf_for_anv_image(cmd_buffer->device,
dst_image, 1U << aspect_bit,
+ VK_IMAGE_USAGE_TRANSFER_DST_BIT,
dstImageLayout, ISL_AUX_USAGE_NONE, &dst);
struct anv_format_plane src_format =
blorp_batch_finish(&batch);
}
-static enum isl_format
-isl_format_for_size(unsigned size_B)
-{
- switch (size_B) {
- case 4: return ISL_FORMAT_R32_UINT;
- case 8: return ISL_FORMAT_R32G32_UINT;
- case 16: return ISL_FORMAT_R32G32B32A32_UINT;
- default:
- unreachable("Not a power-of-two format size");
- }
-}
-
/**
* Returns the greatest common divisor of a and b that is a power of two.
*/
struct blorp_address src = {
.buffer = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
.offset = tmp_data.offset,
- .mocs = cmd_buffer->device->default_mocs,
+ .mocs = cmd_buffer->device->isl_dev.mocs.internal,
};
struct blorp_address dst = {
.buffer = dst_buffer->address.bo,
struct blorp_surf surf;
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, pRanges[r].aspectMask,
+ VK_IMAGE_USAGE_TRANSFER_DST_BIT,
imageLayout, ISL_AUX_USAGE_NONE, &surf);
struct anv_format_plane src_format =
if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, VK_IMAGE_ASPECT_DEPTH_BIT,
+ VK_IMAGE_USAGE_TRANSFER_DST_BIT,
imageLayout, ISL_AUX_USAGE_NONE, &depth);
} else {
memset(&depth, 0, sizeof(depth));
if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, VK_IMAGE_ASPECT_STENCIL_BIT,
+ VK_IMAGE_USAGE_TRANSFER_DST_BIT,
imageLayout, ISL_AUX_USAGE_NONE, &stencil);
has_stencil_shadow =
struct blorp_surf src_surf, dst_surf;
get_blorp_surf_for_anv_image(cmd_buffer->device, src_image, aspect,
- ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
+ 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
src_aux_usage, &src_surf);
if (src_aux_usage == ISL_AUX_USAGE_MCS) {
src_surf.clear_color_addr = anv_to_blorp_address(
VK_IMAGE_ASPECT_COLOR_BIT));
}
get_blorp_surf_for_anv_image(cmd_buffer->device, dst_image, aspect,
- ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
+ 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
dst_aux_usage, &dst_surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
aspect, dst_aux_usage,
pRegions[r].srcSubresource.aspectMask) {
enum isl_aux_usage src_aux_usage =
anv_layout_to_aux_usage(&cmd_buffer->device->info, src_image,
- (1 << aspect_bit), srcImageLayout);
+ (1 << aspect_bit),
+ VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
+ srcImageLayout);
enum isl_aux_usage dst_aux_usage =
anv_layout_to_aux_usage(&cmd_buffer->device->info, dst_image,
- (1 << aspect_bit), dstImageLayout);
+ (1 << aspect_bit),
+ VK_IMAGE_USAGE_TRANSFER_DST_BIT,
+ dstImageLayout);
anv_image_msaa_resolve(cmd_buffer,
src_image, src_aux_usage,
}
}
-static enum isl_aux_usage
-fast_clear_aux_usage(const struct anv_image *image,
- VkImageAspectFlagBits aspect)
-{
- uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
- if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
- return ISL_AUX_USAGE_CCS_D;
- else
- return image->planes[plane].aux_usage;
-}
-
void
anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
struct blorp_surf surf;
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, aspect,
+ VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
VK_IMAGE_LAYOUT_GENERAL,
ISL_AUX_USAGE_NONE, &surf);
assert(surf.aux_usage == ISL_AUX_USAGE_NONE);
struct blorp_surf surf;
get_blorp_surf_for_anv_image(cmd_buffer->device, image, aspect,
- ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
+ 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
aux_usage, &surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, image, aspect, aux_usage,
level, base_layer, layer_count);
if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, VK_IMAGE_ASPECT_DEPTH_BIT,
- ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
+ 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
depth_aux_usage, &depth);
depth.clear_color.f32[0] = ANV_HZ_FC_VAL;
}
if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, VK_IMAGE_ASPECT_STENCIL_BIT,
- ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
+ 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
ISL_AUX_USAGE_NONE, &stencil);
}
* cache before rendering to it.
*/
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
blorp_clear_depth_stencil(&batch, &depth, &stencil,
level, base_layer, layer_count,
* cache before someone starts trying to do stencil on it.
*/
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
struct blorp_surf stencil_shadow;
if ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
{
assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
assert(base_layer + layer_count <= anv_image_aux_layers(image, aspect, level));
- assert(anv_image_aspect_to_plane(image->aspects,
- VK_IMAGE_ASPECT_DEPTH_BIT) == 0);
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+ assert(plane == 0);
struct blorp_batch batch;
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
struct blorp_surf surf;
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, VK_IMAGE_ASPECT_DEPTH_BIT,
- ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
- ISL_AUX_USAGE_HIZ, &surf);
+ 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
+ image->planes[plane].aux_usage, &surf);
surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
blorp_hiz_op(&batch, &surf, level, base_layer, layer_count, hiz_op);
struct blorp_surf depth = {};
if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects,
+ VK_IMAGE_ASPECT_DEPTH_BIT);
assert(base_layer + layer_count <=
anv_image_aux_layers(image, VK_IMAGE_ASPECT_DEPTH_BIT, level));
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, VK_IMAGE_ASPECT_DEPTH_BIT,
- ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
- ISL_AUX_USAGE_HIZ, &depth);
+ 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
+ image->planes[plane].aux_usage, &depth);
depth.clear_color.f32[0] = ANV_HZ_FC_VAL;
}
struct blorp_surf stencil = {};
if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects,
+ VK_IMAGE_ASPECT_STENCIL_BIT);
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, VK_IMAGE_ASPECT_STENCIL_BIT,
- ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
- ISL_AUX_USAGE_NONE, &stencil);
+ 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
+ image->planes[plane].aux_usage, &stencil);
}
/* From the Sky Lake PRM Volume 7, "Depth Buffer Clear":
void
anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
- enum isl_format format,
+ enum isl_format format, struct isl_swizzle swizzle,
VkImageAspectFlagBits aspect,
uint32_t base_layer, uint32_t layer_count,
enum isl_aux_op mcs_op, union isl_color_value *clear_value,
struct blorp_surf surf;
get_blorp_surf_for_anv_image(cmd_buffer->device, image, aspect,
- ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
+ 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
ISL_AUX_USAGE_MCS, &surf);
/* Blorp will store the clear color for us if we provide the clear color
* that it is completed before any additional drawing occurs.
*/
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
switch (mcs_op) {
case ISL_AUX_OP_FAST_CLEAR:
- blorp_fast_clear(&batch, &surf, format,
+ blorp_fast_clear(&batch, &surf, format, swizzle,
0, base_layer, layer_count,
0, 0, image->extent.width, image->extent.height);
break;
}
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
blorp_batch_finish(&batch);
}
void
anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
- enum isl_format format,
+ enum isl_format format, struct isl_swizzle swizzle,
VkImageAspectFlagBits aspect, uint32_t level,
uint32_t base_layer, uint32_t layer_count,
enum isl_aux_op ccs_op, union isl_color_value *clear_value,
struct blorp_surf surf;
get_blorp_surf_for_anv_image(cmd_buffer->device, image, aspect,
- ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
- fast_clear_aux_usage(image, aspect),
+ 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
+ image->planes[plane].aux_usage,
&surf);
/* Blorp will store the clear color for us if we provide the clear color
* that it is completed before any additional drawing occurs.
*/
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
switch (ccs_op) {
case ISL_AUX_OP_FAST_CLEAR:
- blorp_fast_clear(&batch, &surf, format,
+ blorp_fast_clear(&batch, &surf, format, swizzle,
level, base_layer, layer_count,
0, 0, level_width, level_height);
break;
}
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
blorp_batch_finish(&batch);
}
projects / mesa.git / blobdiff