Introduce .editorconfig

[mesa.git] / src / mesa / drivers / dri / i915 / i915_reg.h

diff --git a/src/mesa/drivers/dri/i915/i915_reg.h b/src/mesa/drivers/dri/i915/i915_reg.h
index b5fa7fddb9636f186ce715e57b45db6f4c181219..e09f1f1f9c83478a1cf949ef3044acb062d7dab0 100644 (file)
--- a/src/mesa/drivers/dri/i915/i915_reg.h
+++ b/src/mesa/drivers/dri/i915/i915_reg.h
@@ -1,6 +1,6 @@
 /**************************************************************************
  * 
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2003 VMware, Inc.
  * All Rights Reserved.
  * 
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -18,7 +18,7 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -361,13 +361,6 @@
 /* p222 */
 
 
-#define I915_MAX_TEX_INDIRECT 4
-#define I915_MAX_TEX_INSN     32
-#define I915_MAX_ALU_INSN     64
-#define I915_MAX_DECL_INSN    27
-#define I915_MAX_TEMPORARY    16
-
-
 /* Each instruction is 3 dwords long, though most don't require all
  * this space.  Maximum of 123 instructions.  Smaller maxes per insn
  * type.
@@ -626,9 +619,9 @@
 #define    MT_32BIT_AWVU2101010                   (0xA<<3)
 #define    MT_32BIT_GR1616                (0xB<<3)
 #define    MT_32BIT_VU1616                (0xC<<3)
-#define    MT_32BIT_xI824                 (0xD<<3)
-#define    MT_32BIT_xA824                 (0xE<<3)
-#define    MT_32BIT_xL824                 (0xF<<3)
+#define    MT_32BIT_x8I24                 (0xD<<3)
+#define    MT_32BIT_x8L24                 (0xE<<3)
+#define    MT_32BIT_x8A24                 (0xF<<3)
 #define    MT_422_YCRCB_SWAPY             (0<<3)       /* SURFACE_422 */
 #define    MT_422_YCRCB_NORMAL            (1<<3)
 #define    MT_422_YCRCB_SWAPUV            (2<<3)