#include "intel_span.h"
#include "tnl/t_pipeline.h"
-
/***************************************
* Mesa's Driver Functions
***************************************/
brwInitFragProgFuncs( functions );
brw_init_queryobj_functions(functions);
-
- functions->Enable = brw_enable;
- functions->DepthRange = brw_depth_range;
}
GLboolean brwCreateContext( int api,
- const __GLcontextModes *mesaVis,
+ const struct gl_config *mesaVis,
__DRIcontext *driContextPriv,
void *sharedContextPrivate)
{
struct dd_function_table functions;
struct brw_context *brw = (struct brw_context *) CALLOC_STRUCT(brw_context);
struct intel_context *intel = &brw->intel;
- GLcontext *ctx = &intel->ctx;
+ struct gl_context *ctx = &intel->ctx;
unsigned i;
if (!brw) {
ctx->Const.MaxVertexTextureImageUnits +
ctx->Const.MaxTextureImageUnits;
- /* Mesa limits textures to 4kx4k; it would be nice to fix that someday
- */
- ctx->Const.MaxTextureLevels = 13;
+ ctx->Const.MaxTextureLevels = 14; /* 8192 */
+ if (ctx->Const.MaxTextureLevels > MAX_TEXTURE_LEVELS)
+ ctx->Const.MaxTextureLevels = MAX_TEXTURE_LEVELS;
ctx->Const.Max3DTextureLevels = 9;
ctx->Const.MaxCubeTextureLevels = 12;
ctx->Const.MaxTextureRectSize = (1<<12);
MIN2(ctx->Const.FragmentProgram.MaxNativeParameters,
ctx->Const.FragmentProgram.MaxEnvParams);
+ /* Fragment shaders use real, 32-bit twos-complement integers for all
+ * integer types.
+ */
+ ctx->Const.FragmentProgram.LowInt.RangeMin = 31;
+ ctx->Const.FragmentProgram.LowInt.RangeMax = 30;
+ ctx->Const.FragmentProgram.LowInt.Precision = 0;
+ ctx->Const.FragmentProgram.HighInt = ctx->Const.FragmentProgram.MediumInt
+ = ctx->Const.FragmentProgram.LowInt;
+
+ /* Gen6 converts quads to polygon in beginning of 3D pipeline,
+ but we're not sure how it's actually done for vertex order,
+ that affect provoking vertex decision. Always use last vertex
+ convention for quad primitive which works as expected for now. */
+ if (intel->gen >= 6)
+ ctx->Const.QuadsFollowProvokingVertexConvention = GL_FALSE;
+
if (intel->is_g4x || intel->gen >= 5) {
brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_GM45;
brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
}
/* WM maximum threads is number of EUs times number of threads per EU. */
- if (intel->gen >= 6) {
- brw->urb.size = 1024;
- brw->vs_max_threads = 60;
- brw->wm_max_threads = 80;
+ if (intel->gen >= 7) {
+ if (IS_IVB_GT1(intel->intelScreen->deviceID)) {
+ brw->wm_max_threads = 86;
+ brw->vs_max_threads = 36;
+ brw->urb.size = 128;
+ brw->urb.max_vs_entries = 512;
+ brw->urb.max_gs_entries = 192;
+ } else if (IS_IVB_GT2(intel->intelScreen->deviceID)) {
+ brw->wm_max_threads = 86;
+ brw->vs_max_threads = 128;
+ brw->urb.size = 256;
+ brw->urb.max_vs_entries = 704;
+ brw->urb.max_gs_entries = 320;
+ } else {
+ assert(!"Unknown gen7 device.");
+ }
+ } else if (intel->gen == 6) {
+ if (IS_SNB_GT2(intel->intelScreen->deviceID)) {
+ /* This could possibly be 80, but is supposed to require
+ * disabling of WIZ hashing (bit 6 of GT_MODE, 0x20d0) and a
+ * GPU reset to change.
+ */
+ brw->wm_max_threads = 40;
+ brw->vs_max_threads = 60;
+ brw->urb.size = 64; /* volume 5c.5 section 5.1 */
+ brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
+ } else {
+ brw->wm_max_threads = 40;
+ brw->vs_max_threads = 24;
+ brw->urb.size = 32; /* volume 5c.5 section 5.1 */
+ brw->urb.max_vs_entries = 128; /* volume 2a (see 3DSTATE_URB) */
+ }
} else if (intel->gen == 5) {
brw->urb.size = 1024;
brw->vs_max_threads = 72;
brw->emit_state_always = 0;
+ intel->batch.need_workaround_flush = true;
+
ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
brw_draw_init( brw );
- /* Now that most driver functions are hooked up, initialize some of the
- * immediate state.
- */
- brw_update_cc_vp(brw);
-
return GL_TRUE;
}