i965: Calculate thread_count in brw_alloc_stage_scratch

[mesa.git] / src / mesa / drivers / dri / i965 / brw_cs.c

diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/drivers/dri/i965/brw_cs.c
index 1a0e9f62c631e0556243f565780692b5a71d32f6..1d34a8a79d18cd18b58f218decd0c25a05c93788 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -114,29 +114,7 @@ brw_codegen_cs_prog(struct brw_context *brw,
       }
    }
 
-   const unsigned subslices = MAX2(brw->screen->subslice_total, 1);
-
-   /* WaCSScratchSize:hsw
-    *
-    * Haswell's scratch space address calculation appears to be sparse
-    * rather than tightly packed.  The Thread ID has bits indicating
-    * which subslice, EU within a subslice, and thread within an EU
-    * it is.  There's a maximum of two slices and two subslices, so these
-    * can be stored with a single bit.  Even though there are only 10 EUs
-    * per subslice, this is stored in 4 bits, so there's an effective
-    * maximum value of 16 EUs.  Similarly, although there are only 7
-    * threads per EU, this is stored in a 3 bit number, giving an effective
-    * maximum value of 8 threads per EU.
-    *
-    * This means that we need to use 16 * 8 instead of 10 * 7 for the
-    * number of threads per subslice.
-    */
-   const unsigned scratch_ids_per_subslice =
-      devinfo->is_haswell ? 16 * 8 : devinfo->max_cs_threads;
-
-   brw_alloc_stage_scratch(brw, &brw->cs.base,
-                           prog_data.base.total_scratch,
-                           scratch_ids_per_subslice * subslices);
+   brw_alloc_stage_scratch(brw, &brw->cs.base, prog_data.base.total_scratch);
 
    /* The param and pull_param arrays will be freed by the shader cache. */
    ralloc_steal(NULL, prog_data.base.param);