Merge branch 'master' of ../mesa into vulkan

[mesa.git] / src / mesa / drivers / dri / i965 / brw_nir.c

diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c
index 1d4f6ab2ccd5e257a4c11889f1178d92db1c96c9..35855092dfff4f8cc4f69bd4a96d527d588f4b9f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -80,11 +80,7 @@ brw_create_nir(struct brw_context *brw,
    struct gl_context *ctx = &brw->ctx;
    const nir_shader_compiler_options *options =
       ctx->Const.ShaderCompilerOptions[stage].NirOptions;
-   static const nir_lower_tex_options tex_options = {
-      .lower_txp = ~0,
-   };
    struct gl_shader *shader = shader_prog ? shader_prog->_LinkedShaders[stage] : NULL;
-   bool debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
    nir_shader *nir;
 
    /* First, lower the GLSL IR or Mesa IR to NIR */
@@ -96,6 +92,30 @@ brw_create_nir(struct brw_context *brw,
    }
    nir_validate_shader(nir);
 
+   brw_process_nir(nir, brw->intelScreen->devinfo, shader_prog, stage, is_scalar);
+
+   static GLuint msg_id = 0;
+   _mesa_gl_debug(&brw->ctx, &msg_id,
+                  MESA_DEBUG_SOURCE_SHADER_COMPILER,
+                  MESA_DEBUG_TYPE_OTHER,
+                  MESA_DEBUG_SEVERITY_NOTIFICATION,
+                  "%s NIR shader:\n",
+                  _mesa_shader_stage_to_abbrev(stage));
+
+   return nir;
+}
+
+void
+brw_process_nir(nir_shader *nir,
+                const struct brw_device_info *devinfo,
+                const struct gl_shader_program *shader_prog,
+                gl_shader_stage stage, bool is_scalar)
+{
+   bool debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
+   static const nir_lower_tex_options tex_options = {
+      .lower_txp = ~0,
+   };
+
    if (stage == MESA_SHADER_GEOMETRY) {
       nir_lower_gs_intrinsics(nir);
       nir_validate_shader(nir);
@@ -149,8 +169,10 @@ brw_create_nir(struct brw_context *brw,
 
    if (shader_prog) {
       nir_lower_samplers(nir, shader_prog);
-      nir_validate_shader(nir);
+   } else {
+      nir_lower_samplers_for_vk(nir);
    }
+   nir_validate_shader(nir);
 
    nir_lower_system_values(nir);
    nir_validate_shader(nir);
@@ -160,7 +182,7 @@ brw_create_nir(struct brw_context *brw,
 
    nir_optimize(nir, is_scalar);
 
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       /* Try and fuse multiply-adds */
       nir_opt_peephole_ffma(nir);
       nir_validate_shader(nir);
@@ -207,7 +229,7 @@ brw_create_nir(struct brw_context *brw,
     * run it last because it stashes data in instr->pass_flags and we don't
     * want that to be squashed by other NIR passes.
     */
-   if (brw->gen <= 5)
+   if (devinfo->gen <= 5)
       brw_nir_analyze_boolean_resolves(nir);
 
    nir_sweep(nir);
@@ -217,8 +239,6 @@ brw_create_nir(struct brw_context *brw,
               _mesa_shader_stage_to_string(stage));
       nir_print_shader(nir, stderr);
    }
-
-   return nir;
 }
 
 enum brw_reg_type