* IN THE SOFTWARE.
*/
-#include "main/macros.h"
#include "brw_context.h"
-#include "brw_vs.h"
-#include "brw_gs.h"
-#include "brw_fs.h"
#include "brw_cfg.h"
+#include "brw_eu.h"
#include "brw_nir.h"
-#include "glsl/ir_optimization.h"
#include "glsl/glsl_parser_extras.h"
-#include "main/shaderapi.h"
+#include "main/shaderobj.h"
+#include "main/uniforms.h"
+#include "util/debug.h"
static void
shader_debug_log_mesa(void *data, const char *fmt, ...)
va_end(args);
}
-bool
-is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
-{
- switch (stage) {
- case MESA_SHADER_FRAGMENT:
- case MESA_SHADER_COMPUTE:
- return true;
- case MESA_SHADER_GEOMETRY:
- return compiler->scalar_gs;
- case MESA_SHADER_VERTEX:
- return compiler->scalar_vs;
- default:
- return false;
- }
-}
-
struct brw_compiler *
brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
{
brw_fs_alloc_reg_sets(compiler);
brw_vec4_alloc_reg_set(compiler);
- if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
- compiler->scalar_vs = true;
-
- if (devinfo->gen >= 8 && brw_env_var_as_boolean("INTEL_SCALAR_GS", false))
- compiler->scalar_gs = true;
+ compiler->scalar_stage[MESA_SHADER_VERTEX] =
+ devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
+ compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
+ devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
+ compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
+ compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
nir_shader_compiler_options *nir_options =
rzalloc(compiler, nir_shader_compiler_options);
*/
nir_options->lower_ffma = true;
nir_options->lower_sub = true;
+ nir_options->lower_fdiv = true;
+
/* In the vec4 backend, our dpN instruction replicates its result to all
* the components of a vec4. We would like NIR to give us replicated fdot
* instructions because it can optimize better for us.
compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
compiler->glsl_compiler_options[i].LowerClipDistance = true;
- bool is_scalar = is_scalar_shader_stage(compiler, i);
+ bool is_scalar = compiler->scalar_stage[i];
compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
}
+ if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
+ compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
+
+ compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
+ .LowerShaderSharedVariables = true;
+
return compiler;
}
-struct gl_shader *
+extern "C" struct gl_shader *
brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
{
struct brw_shader *shader;
return &shader->base;
}
-void
+extern "C" void
brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
unsigned surf_index)
{
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
case GLSL_TYPE_DOUBLE:
+ case GLSL_TYPE_FUNCTION:
unreachable("not reached");
}
return "gen8_urb_write_simd8_masked_per_slot";
case SHADER_OPCODE_URB_READ_SIMD8:
return "urb_read_simd8";
+ case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
+ return "urb_read_simd8_per_slot";
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
return "find_live_channel";
return "barrier";
case SHADER_OPCODE_MULH:
return "mulh";
+ case SHADER_OPCODE_MOV_INDIRECT:
+ return "mov_indirect";
}
unreachable("not reached");
unsigned ud;
int d;
float f;
- } imm = { reg->dw1.ud }, sat_imm = { 0 };
+ } imm = { reg->ud }, sat_imm = { 0 };
switch (type) {
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_D:
+ case BRW_REGISTER_TYPE_UW:
+ case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
/* Nothing to do. */
return false;
- case BRW_REGISTER_TYPE_UW:
- sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
- break;
- case BRW_REGISTER_TYPE_W:
- sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
- break;
case BRW_REGISTER_TYPE_F:
sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
break;
}
if (imm.ud != sat_imm.ud) {
- reg->dw1.ud = sat_imm.ud;
+ reg->ud = sat_imm.ud;
return true;
}
return false;
switch (type) {
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UD:
- reg->dw1.d = -reg->dw1.d;
+ reg->d = -reg->d;
return true;
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW:
- reg->dw1.d = -(int16_t)reg->dw1.ud;
+ reg->d = -(int16_t)reg->ud;
return true;
case BRW_REGISTER_TYPE_F:
- reg->dw1.f = -reg->dw1.f;
+ reg->f = -reg->f;
return true;
case BRW_REGISTER_TYPE_VF:
- reg->dw1.ud ^= 0x80808080;
+ reg->ud ^= 0x80808080;
return true;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
{
switch (type) {
case BRW_REGISTER_TYPE_D:
- reg->dw1.d = abs(reg->dw1.d);
+ reg->d = abs(reg->d);
return true;
case BRW_REGISTER_TYPE_W:
- reg->dw1.d = abs((int16_t)reg->dw1.ud);
+ reg->d = abs((int16_t)reg->ud);
return true;
case BRW_REGISTER_TYPE_F:
- reg->dw1.f = fabsf(reg->dw1.f);
+ reg->f = fabsf(reg->f);
return true;
case BRW_REGISTER_TYPE_VF:
- reg->dw1.ud &= ~0x80808080;
+ reg->ud &= ~0x80808080;
return true;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
}
+bool
+backend_reg::equals(const backend_reg &r) const
+{
+ return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
+ reg_offset == r.reg_offset;
+}
+
bool
backend_reg::is_zero() const
{
if (file != IMM)
return false;
- return fixed_hw_reg.dw1.d == 0;
+ return d == 0;
}
bool
return false;
return type == BRW_REGISTER_TYPE_F
- ? fixed_hw_reg.dw1.f == 1.0
- : fixed_hw_reg.dw1.d == 1;
+ ? f == 1.0
+ : d == 1;
}
bool
switch (type) {
case BRW_REGISTER_TYPE_F:
- return fixed_hw_reg.dw1.f == -1.0;
+ return f == -1.0;
case BRW_REGISTER_TYPE_D:
- return fixed_hw_reg.dw1.d == -1;
+ return d == -1;
default:
return false;
}
bool
backend_reg::is_null() const
{
- return file == HW_REG &&
- fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
- fixed_hw_reg.nr == BRW_ARF_NULL;
+ return file == ARF && nr == BRW_ARF_NULL;
}
bool
backend_reg::is_accumulator() const
{
- return file == HW_REG &&
- fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
- fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
+ return file == ARF && nr == BRW_ARF_ACCUMULATOR;
}
bool
backend_reg::in_range(const backend_reg &r, unsigned n) const
{
return (file == r.file &&
- reg == r.reg &&
+ nr == r.nr &&
reg_offset >= r.reg_offset &&
reg_offset < r.reg_offset + n);
}
projects / mesa.git / blobdiff