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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4.h
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index d861b2e85dfb64600f1d527026f661d5d414ad5a..f94f7128a07681c2ad82ddb3f2ce9437b26e2558 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -52,6 +52,15 @@ extern "C" {
 extern "C" {
 #endif
 
+const unsigned *
+brw_vec4_generate_assembly(const struct brw_compiler *compiler,
+                           void *log_data,
+                           void *mem_ctx,
+                           const nir_shader *nir,
+                           struct brw_vue_prog_data *prog_data,
+                           const struct cfg_t *cfg,
+                           unsigned *out_assembly_size);
+
 #ifdef __cplusplus
 } /* extern "C" */
 
@@ -149,6 +158,7 @@ public:
    int var_range_start(unsigned v, unsigned n) const;
    int var_range_end(unsigned v, unsigned n) const;
    bool virtual_grf_interferes(int a, int b);
+   bool opt_cmod_propagation();
    bool opt_copy_propagation(bool do_constant_prop = true);
    bool opt_cse_local(bblock_t *block);
    bool opt_cse();
@@ -158,6 +168,7 @@ public:
    bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
    void opt_set_dependency_control();
    void opt_schedule_instructions();
+   void convert_to_hw_regs();
 
    vec4_instruction *emit(vec4_instruction *inst);
 
@@ -262,15 +273,12 @@ public:
                      src_reg offset_value,
                      src_reg mcs,
                      bool is_cube_array,
+                     uint32_t surface, src_reg surface_reg,
                      uint32_t sampler, src_reg sampler_reg);
 
-   uint32_t gather_channel(unsigned gather_component, uint32_t sampler);
    src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate,
                           src_reg sampler);
    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
-   void swizzle_result(ir_texture_opcode op, dst_reg dest,
-                       src_reg orig_val, uint32_t sampler,
-                       const glsl_type *dest_type);
 
    void emit_ndc_computation();
    void emit_psiz_and_flags(dst_reg reg);
@@ -381,117 +389,6 @@ private:
    unsigned last_scratch; /**< measured in 32-byte (register size) units */
 };
 
-
-/**
- * The vertex shader code generator.
- *
- * Translates VS IR to actual i965 assembly code.
- */
-class vec4_generator
-{
-public:
-   vec4_generator(const struct brw_compiler *compiler, void *log_data,
-                  struct brw_vue_prog_data *prog_data,
-                  void *mem_ctx,
-                  bool debug_flag,
-                  const char *stage_name,
-                  const char *stage_abbrev);
-   ~vec4_generator();
-
-   const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size,
-                                     const nir_shader *nir);
-
-private:
-   void generate_code(const cfg_t *cfg, const nir_shader *nir);
-
-   void generate_math1_gen4(vec4_instruction *inst,
-                           struct brw_reg dst,
-                           struct brw_reg src);
-   void generate_math2_gen4(vec4_instruction *inst,
-                           struct brw_reg dst,
-                           struct brw_reg src0,
-                           struct brw_reg src1);
-   void generate_math_gen6(vec4_instruction *inst,
-                           struct brw_reg dst,
-                           struct brw_reg src0,
-                           struct brw_reg src1);
-
-   void generate_tex(vec4_instruction *inst,
-                     struct brw_reg dst,
-                     struct brw_reg src,
-                     struct brw_reg sampler_index);
-
-   void generate_vs_urb_write(vec4_instruction *inst);
-   void generate_gs_urb_write(vec4_instruction *inst);
-   void generate_gs_urb_write_allocate(vec4_instruction *inst);
-   void generate_gs_thread_end(vec4_instruction *inst);
-   void generate_gs_set_write_offset(struct brw_reg dst,
-                                     struct brw_reg src0,
-                                     struct brw_reg src1);
-   void generate_gs_set_vertex_count(struct brw_reg dst,
-                                     struct brw_reg src);
-   void generate_gs_svb_write(vec4_instruction *inst,
-                              struct brw_reg dst,
-                              struct brw_reg src0,
-                              struct brw_reg src1);
-   void generate_gs_svb_set_destination_index(vec4_instruction *inst,
-                                              struct brw_reg dst,
-                                              struct brw_reg src);
-   void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
-   void generate_gs_prepare_channel_masks(struct brw_reg dst);
-   void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
-   void generate_gs_get_instance_id(struct brw_reg dst);
-   void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
-                                           struct brw_reg src0,
-                                           struct brw_reg src1,
-                                           struct brw_reg src2);
-   void generate_gs_ff_sync(vec4_instruction *inst,
-                            struct brw_reg dst,
-                            struct brw_reg src0,
-                            struct brw_reg src1);
-   void generate_gs_set_primitive_id(struct brw_reg dst);
-   void generate_oword_dual_block_offsets(struct brw_reg m1,
-                                         struct brw_reg index);
-   void generate_scratch_write(vec4_instruction *inst,
-                              struct brw_reg dst,
-                              struct brw_reg src,
-                              struct brw_reg index);
-   void generate_scratch_read(vec4_instruction *inst,
-                             struct brw_reg dst,
-                             struct brw_reg index);
-   void generate_pull_constant_load(vec4_instruction *inst,
-                                   struct brw_reg dst,
-                                   struct brw_reg index,
-                                   struct brw_reg offset);
-   void generate_pull_constant_load_gen7(vec4_instruction *inst,
-                                         struct brw_reg dst,
-                                         struct brw_reg surf_index,
-                                         struct brw_reg offset);
-   void generate_set_simd4x2_header_gen9(vec4_instruction *inst,
-                                         struct brw_reg dst);
-
-   void generate_get_buffer_size(vec4_instruction *inst,
-                                 struct brw_reg dst,
-                                 struct brw_reg src,
-                                 struct brw_reg index);
-
-   void generate_unpack_flags(struct brw_reg dst);
-
-   const struct brw_compiler *compiler;
-   void *log_data; /* Passed to compiler->*_log functions */
-
-   const struct brw_device_info *devinfo;
-
-   struct brw_codegen *p;
-
-   struct brw_vue_prog_data *prog_data;
-
-   void *mem_ctx;
-   const char *stage_name;
-   const char *stage_abbrev;
-   const bool debug_flag;
-};
-
 } /* namespace brw */
 #endif /* __cplusplus */