#include "brw_vec4.h"
#include "brw_vec4_builder.h"
#include "brw_vec4_surface_builder.h"
-#include "glsl/ir_uniform.h"
+#include "brw_program.h"
using namespace brw;
using namespace brw::surface_access;
void
vec4_visitor::emit_nir_code()
{
- if (nir->num_inputs > 0)
- nir_setup_inputs();
-
if (nir->num_uniforms > 0)
nir_setup_uniforms();
}
}
-void
-vec4_visitor::nir_setup_inputs()
-{
- nir_inputs = ralloc_array(mem_ctx, src_reg, nir->num_inputs);
- for (unsigned i = 0; i < nir->num_inputs; i++) {
- nir_inputs[i] = src_reg();
- }
-
- nir_foreach_variable(var, &nir->inputs) {
- int offset = var->data.driver_location;
- unsigned size = type_size_vec4(var->type);
- for (unsigned i = 0; i < size; i++) {
- src_reg src = src_reg(ATTR, var->data.location + i, var->type);
- nir_inputs[offset + i] = src;
- }
- }
-}
-
void
vec4_visitor::nir_setup_uniforms()
{
- uniforms = nir->num_uniforms;
+ uniforms = nir->num_uniforms / 16;
nir_foreach_variable(var, &nir->uniforms) {
/* UBO's and atomics don't take up space in the uniform file */
continue;
if (type_size_vec4(var->type) > 0)
- uniform_size[var->data.driver_location] = type_size_vec4(var->type);
+ uniform_size[var->data.driver_location / 16] = type_size_vec4(var->type);
}
}
dst_reg dest;
src_reg src;
- bool has_indirect = false;
-
switch (instr->intrinsic) {
- case nir_intrinsic_load_input_indirect:
- has_indirect = true;
- /* fallthrough */
case nir_intrinsic_load_input: {
- int offset = instr->const_index[0];
- src = nir_inputs[offset];
+ nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
+
+ /* We set EmitNoIndirectInput for VS */
+ assert(const_offset);
+
+ src = src_reg(ATTR, instr->const_index[0] + const_offset->u[0],
+ glsl_type::uvec4_type);
- if (has_indirect) {
- dest.reladdr = new(mem_ctx) src_reg(get_nir_src(instr->src[0],
- BRW_REGISTER_TYPE_D,
- 1));
- }
dest = get_nir_dest(instr->dest, src.type);
dest.writemask = brw_writemask_for_size(instr->num_components);
break;
}
- case nir_intrinsic_store_output_indirect:
- has_indirect = true;
- /* fallthrough */
case nir_intrinsic_store_output: {
- int varying = instr->const_index[0];
+ nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
+ assert(const_offset);
+
+ int varying = instr->const_index[0] + const_offset->u[0];
src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F,
instr->num_components);
- dest = dst_reg(src);
- if (has_indirect) {
- dest.reladdr = new(mem_ctx) src_reg(get_nir_src(instr->src[1],
- BRW_REGISTER_TYPE_D,
- 1));
- }
- output_reg[varying] = dest;
+ output_reg[varying] = dst_reg(src);
break;
}
break;
}
- case nir_intrinsic_store_ssbo_indirect:
- has_indirect = true;
- /* fallthrough */
case nir_intrinsic_store_ssbo: {
assert(devinfo->gen >= 7);
}
/* Offset */
- src_reg offset_reg = src_reg(this, glsl_type::uint_type);
- unsigned const_offset_bytes = 0;
- if (has_indirect) {
- emit(MOV(dst_reg(offset_reg), get_nir_src(instr->src[2], 1)));
+ src_reg offset_reg;
+ nir_const_value *const_offset = nir_src_as_const_value(instr->src[2]);
+ if (const_offset) {
+ offset_reg = brw_imm_ud(const_offset->u[0]);
} else {
- const_offset_bytes = instr->const_index[0];
- emit(MOV(dst_reg(offset_reg), brw_imm_ud(const_offset_bytes)));
+ offset_reg = get_nir_src(instr->src[2], 1);
}
/* Value */
src_reg val_reg = get_nir_src(instr->src[0], 4);
/* Writemask */
- unsigned write_mask = instr->const_index[1];
+ unsigned write_mask = instr->const_index[0];
/* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
* writes will use SIMD8 mode. In order to hide this and keep symmetry across
* write at to skip the channels we skipped, if any.
*/
if (skipped_channels > 0) {
- if (!has_indirect) {
- const_offset_bytes += 4 * skipped_channels;
- offset_reg = brw_imm_ud(const_offset_bytes);
+ if (offset_reg.file == IMM) {
+ offset_reg.ud += 4 * skipped_channels;
} else {
emit(ADD(dst_reg(offset_reg), offset_reg,
brw_imm_ud(4 * skipped_channels)));
break;
}
- case nir_intrinsic_load_ssbo_indirect:
- has_indirect = true;
- /* fallthrough */
case nir_intrinsic_load_ssbo: {
assert(devinfo->gen >= 7);
nir->info.num_ssbos - 1);
}
- src_reg offset_reg = src_reg(this, glsl_type::uint_type);
- unsigned const_offset_bytes = 0;
- if (has_indirect) {
- emit(MOV(dst_reg(offset_reg), get_nir_src(instr->src[1], 1)));
+ src_reg offset_reg;
+ nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
+ if (const_offset) {
+ offset_reg = brw_imm_ud(const_offset->u[0]);
} else {
- const_offset_bytes = instr->const_index[0];
- emit(MOV(dst_reg(offset_reg), brw_imm_ud((const_offset_bytes))));
+ offset_reg = get_nir_src(instr->src[1], 1);
}
/* Read the vector */
break;
}
- case nir_intrinsic_load_uniform_indirect:
- has_indirect = true;
- /* fallthrough */
case nir_intrinsic_load_uniform: {
+ /* Offsets are in bytes but they should always be multiples of 16 */
+ assert(instr->const_index[0] % 16 == 0);
+
dest = get_nir_dest(instr->dest);
- src = src_reg(dst_reg(UNIFORM, instr->const_index[0]));
- src.reg_offset = instr->const_index[1];
+ src = src_reg(dst_reg(UNIFORM, instr->const_index[0] / 16));
+ src.type = dest.type;
- if (has_indirect) {
+ nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
+ if (const_offset) {
+ /* Offsets are in bytes but they should always be multiples of 16 */
+ assert(const_offset->u[0] % 16 == 0);
+ src.reg_offset = const_offset->u[0] / 16;
+ } else {
src_reg tmp = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_D, 1);
src.reladdr = new(mem_ctx) src_reg(tmp);
}
break;
}
- case nir_intrinsic_load_ubo_indirect:
- has_indirect = true;
- /* fallthrough */
case nir_intrinsic_load_ubo: {
nir_const_value *const_block_index = nir_src_as_const_value(instr->src[0]);
src_reg surf_index;
nir->info.num_ubos - 1);
}
- unsigned const_offset = instr->const_index[0];
src_reg offset;
-
- if (!has_indirect) {
- offset = brw_imm_ud(const_offset / 16);
+ nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
+ if (const_offset) {
+ offset = brw_imm_ud(const_offset->u[0] & ~15);
} else {
- offset = src_reg(this, glsl_type::uint_type);
- emit(SHR(dst_reg(offset), get_nir_src(instr->src[1], nir_type_int, 1),
- brw_imm_ud(4u)));
+ offset = get_nir_src(instr->src[1], nir_type_int, 1);
}
src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
NULL, NULL /* before_block/inst */);
packed_consts.swizzle = brw_swizzle_for_size(instr->num_components);
- packed_consts.swizzle += BRW_SWIZZLE4(const_offset % 16 / 4,
- const_offset % 16 / 4,
- const_offset % 16 / 4,
- const_offset % 16 / 4);
+ if (const_offset) {
+ packed_consts.swizzle += BRW_SWIZZLE4(const_offset->u[0] % 16 / 4,
+ const_offset->u[0] % 16 / 4,
+ const_offset->u[0] % 16 / 4,
+ const_offset->u[0] % 16 / 4);
+ }
emit(MOV(dest, packed_consts));
break;