*/
+#include "compiler/nir/nir.h"
#include "main/context.h"
#include "main/blend.h"
#include "main/mtypes.h"
INTEL_AUX_BUFFER_DISABLED = 1 << 1,
};
-struct surface_state_info {
- unsigned num_dwords;
- unsigned ss_align; /* Required alignment of RENDER_SURFACE_STATE in bytes */
- unsigned reloc_dw;
- unsigned aux_reloc_dw;
- unsigned tex_mocs;
- unsigned rb_mocs;
+uint32_t tex_mocs[] = {
+ [7] = GEN7_MOCS_L3,
+ [8] = BDW_MOCS_WB,
+ [9] = SKL_MOCS_WB,
};
-static const struct surface_state_info surface_state_infos[] = {
- [4] = {6, 32, 1, 0},
- [5] = {6, 32, 1, 0},
- [6] = {6, 32, 1, 0},
- [7] = {8, 32, 1, 6, GEN7_MOCS_L3, GEN7_MOCS_L3},
- [8] = {13, 64, 8, 10, BDW_MOCS_WB, BDW_MOCS_PTE},
- [9] = {16, 64, 8, 10, SKL_MOCS_WB, SKL_MOCS_PTE},
+uint32_t rb_mocs[] = {
+ [7] = GEN7_MOCS_L3,
+ [8] = BDW_MOCS_PTE,
+ [9] = SKL_MOCS_PTE,
};
static void
uint32_t mocs, uint32_t *surf_offset, int surf_index,
unsigned read_domains, unsigned write_domains)
{
- const struct surface_state_info ss_info = surface_state_infos[brw->gen];
- uint32_t tile_x = 0, tile_y = 0;
+ uint32_t tile_x = mt->level[0].slice[0].x_offset;
+ uint32_t tile_y = mt->level[0].slice[0].y_offset;
uint32_t offset = mt->offset;
struct isl_surf surf;
surf.dim = get_isl_surf_dim(target);
const enum isl_dim_layout dim_layout =
- get_isl_dim_layout(brw->intelScreen->devinfo, mt->tiling, target);
+ get_isl_dim_layout(&brw->screen->devinfo, mt->tiling, target);
if (surf.dim_layout != dim_layout) {
/* The layout of the specified texture target is not compatible with the
*/
assert(brw->has_surface_tile_offset);
assert(view.levels == 1 && view.array_len == 1);
+ assert(tile_x == 0 && tile_y == 0);
offset += intel_miptree_get_tile_offsets(mt, view.base_level,
view.base_array_layer,
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
+ drm_intel_bo *aux_bo;
struct isl_surf *aux_surf = NULL, aux_surf_s;
uint64_t aux_offset = 0;
enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
- if (mt->mcs_mt && !(flags & INTEL_AUX_BUFFER_DISABLED)) {
+ if ((mt->mcs_buf || intel_miptree_sample_with_hiz(brw, mt)) &&
+ !(flags & INTEL_AUX_BUFFER_DISABLED)) {
intel_miptree_get_aux_isl_surf(brw, mt, &aux_surf_s, &aux_usage);
aux_surf = &aux_surf_s;
- assert(mt->mcs_mt->offset == 0);
- aux_offset = mt->mcs_mt->bo->offset64;
+
+ if (mt->mcs_buf) {
+ assert(mt->mcs_buf->offset == 0);
+ aux_bo = mt->mcs_buf->bo;
+ aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset;
+ } else {
+ aux_bo = mt->hiz_buf->aux_base.bo;
+ aux_offset = mt->hiz_buf->aux_base.bo->offset64 +
+ mt->hiz_buf->mt->offset;
+ }
/* We only really need a clear color if we also have an auxiliary
- * surfacae. Without one, it does nothing.
+ * surface. Without one, it does nothing.
*/
clear_color = intel_miptree_get_isl_clear_color(brw, mt);
}
- uint32_t *dw = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- ss_info.num_dwords * 4, ss_info.ss_align,
- surf_index, surf_offset);
+ void *state = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ brw->isl_dev.ss.size,
+ brw->isl_dev.ss.align,
+ surf_index, surf_offset);
- isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = &view,
+ isl_surf_fill_state(&brw->isl_dev, state, .surf = &surf, .view = &view,
.address = mt->bo->offset64 + offset,
.aux_surf = aux_surf, .aux_usage = aux_usage,
.aux_address = aux_offset,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4 * ss_info.reloc_dw,
+ *surf_offset + brw->isl_dev.ss.addr_offset,
mt->bo, offset,
read_domains, write_domains);
* an ordinary reloc to do the necessary address translation.
*/
assert((aux_offset & 0xfff) == 0);
+ uint32_t *aux_addr = state + brw->isl_dev.ss.aux_addr_offset;
drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4 * ss_info.aux_reloc_dw,
- mt->mcs_mt->bo, dw[ss_info.aux_reloc_dw] & 0xfff,
+ *surf_offset + brw->isl_dev.ss.aux_addr_offset,
+ aux_bo, *aux_addr & 0xfff,
read_domains, write_domains);
}
}
uint32_t offset;
brw_emit_surface_state(brw, mt, flags, mt->target, view,
- surface_state_infos[brw->gen].rb_mocs,
+ rb_mocs[brw->gen],
&offset, surf_index,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
if (!intel_miptree_is_lossless_compressed(brw, mt))
return true;
- if (isl_format_supports_lossless_compression(brw->intelScreen->devinfo,
+ if (isl_format_supports_lossless_compression(&brw->screen->devinfo,
format))
return true;
const struct intel_mipmap_tree *mt)
{
/* Nothing to disable. */
- if (!mt->mcs_mt)
+ if (!mt->mcs_buf)
return false;
/* There are special cases only for lossless compression. */
const int flags =
brw_disable_aux_surface(brw, mt) ? INTEL_AUX_BUFFER_DISABLED : 0;
brw_emit_surface_state(brw, mt, flags, mt->target, view,
- surface_state_infos[brw->gen].tex_mocs,
+ tex_mocs[brw->gen],
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, 0);
}
unsigned pitch,
bool rw)
{
- const struct surface_state_info ss_info = surface_state_infos[brw->gen];
-
uint32_t *dw = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- ss_info.num_dwords * 4, ss_info.ss_align,
+ brw->isl_dev.ss.size,
+ brw->isl_dev.ss.align,
out_offset);
isl_buffer_fill_state(&brw->isl_dev, dw,
.size = buffer_size,
.format = surface_format,
.stride = pitch,
- .mocs = ss_info.tex_mocs);
+ .mocs = tex_mocs[brw->gen]);
if (bo) {
drm_intel_bo_emit_reloc(brw->batch.bo,
- *out_offset + 4 * ss_info.reloc_dw,
+ *out_offset + brw->isl_dev.ss.addr_offset,
bo, buffer_offset,
I915_GEM_DOMAIN_SAMPLER,
(rw ? I915_GEM_DOMAIN_SAMPLER : 0));
{
struct brw_stage_state *stage_state = &brw->wm.base;
/* BRW_NEW_FRAGMENT_PROGRAM */
- struct brw_fragment_program *fp =
- (struct brw_fragment_program *) brw->fragment_program;
+ struct brw_program *fp = (struct brw_program *) brw->fragment_program;
/* BRW_NEW_FS_PROG_DATA */
- struct brw_stage_prog_data *prog_data = &brw->wm.prog_data->base;
+ struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_FRAGMENT);
/* _NEW_PROGRAM_CONSTANTS */
- brw_upload_pull_constants(brw, BRW_NEW_SURFACES, &fp->program.Base,
+ brw_upload_pull_constants(brw, BRW_NEW_SURFACES, &fp->program,
stage_state, prog_data);
}
const uint32_t surf_index = render_target_start + i;
const int flags = (_mesa_geometric_layers(fb) > 0 ?
INTEL_RENDERBUFFER_LAYERED : 0) |
- (brw->draw_aux_buffer_disabled[i] ?
+ (brw->draw_aux_buffer_disabled[i] ?
INTEL_AUX_BUFFER_DISABLED : 0);
if (intel_renderbuffer(fb->_ColorDrawBuffers[i])) {
{
const struct gl_context *ctx = &brw->ctx;
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_wm_prog_data *wm_prog_data =
+ brw_wm_prog_data(brw->wm.base.prog_data);
+
/* _NEW_BUFFERS | _NEW_COLOR */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
brw_update_renderbuffer_surfaces(
brw, fb,
- brw->wm.prog_data->binding_table.render_target_start,
+ wm_prog_data->binding_table.render_target_start,
brw->wm.base.surf_offset);
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
{
const struct gl_context *ctx = &brw->ctx;
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_wm_prog_data *wm_prog_data =
+ brw_wm_prog_data(brw->wm.base.prog_data);
+
/* BRW_NEW_FRAGMENT_PROGRAM */
if (!ctx->Extensions.MESA_shader_framebuffer_fetch &&
- brw->fragment_program &&
- brw->fragment_program->Base.OutputsRead) {
+ brw->fragment_program && brw->fragment_program->info.outputs_read) {
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[i];
const struct intel_renderbuffer *irb = intel_renderbuffer(rb);
const unsigned surf_index =
- brw->wm.prog_data->binding_table.render_target_read_start + i;
+ wm_prog_data->binding_table.render_target_read_start + i;
uint32_t *surf_offset = &brw->wm.base.surf_offset[surf_index];
if (irb) {
const unsigned format = brw->render_target_format[
_mesa_get_render_format(ctx, intel_rb_format(irb))];
- assert(isl_format_supports_sampling(brw->intelScreen->devinfo,
+ assert(isl_format_supports_sampling(&brw->screen->devinfo,
format));
/* Override the target of the texture if the render buffer is a
const int flags = brw->draw_aux_buffer_disabled[i] ?
INTEL_AUX_BUFFER_DISABLED : 0;
brw_emit_surface_state(brw, irb->mt, flags, target, view,
- surface_state_infos[brw->gen].tex_mocs,
+ tex_mocs[brw->gen],
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, 0);
.dirty = {
.mesa = _NEW_BUFFERS,
.brw = BRW_NEW_BATCH |
- BRW_NEW_FRAGMENT_PROGRAM,
+ BRW_NEW_FRAGMENT_PROGRAM |
+ BRW_NEW_FS_PROG_DATA,
},
.emit = update_renderbuffer_read_surfaces,
};
* allows the surface format to be overriden for only the
* gather4 messages. */
if (brw->gen < 8) {
- if (vs && vs->UsesGather)
+ if (vs && vs->nir->info->uses_texture_gather)
update_stage_texture_surfaces(brw, vs, &brw->vs.base, true, 0);
- if (tcs && tcs->UsesGather)
+ if (tcs && tcs->nir->info->uses_texture_gather)
update_stage_texture_surfaces(brw, tcs, &brw->tcs.base, true, 0);
- if (tes && tes->UsesGather)
+ if (tes && tes->nir->info->uses_texture_gather)
update_stage_texture_surfaces(brw, tes, &brw->tes.base, true, 0);
- if (gs && gs->UsesGather)
+ if (gs && gs->nir->info->uses_texture_gather)
update_stage_texture_surfaces(brw, gs, &brw->gs.base, true, 0);
- if (fs && fs->UsesGather)
+ if (fs && fs->nir->info->uses_texture_gather)
update_stage_texture_surfaces(brw, fs, &brw->wm.base, true, 0);
}
* gather4 messages.
*/
if (brw->gen < 8) {
- if (cs && cs->UsesGather)
+ if (cs && cs->nir->info->uses_texture_gather)
update_stage_texture_surfaces(brw, cs, &brw->cs.base, true, 0);
}
/* BRW_NEW_FS_PROG_DATA */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
- &brw->wm.base, &brw->wm.prog_data->base);
+ &brw->wm.base, brw->wm.base.prog_data);
}
const struct brw_tracked_state brw_wm_ubo_surfaces = {
/* BRW_NEW_CS_PROG_DATA */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
- &brw->cs.base, &brw->cs.prog_data->base);
+ &brw->cs.base, brw->cs.base.prog_data);
}
const struct brw_tracked_state brw_cs_ubo_surfaces = {
if (prog) {
/* BRW_NEW_FS_PROG_DATA */
brw_upload_abo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
- &brw->wm.base, &brw->wm.prog_data->base);
+ &brw->wm.base, brw->wm.base.prog_data);
}
}
if (prog) {
/* BRW_NEW_CS_PROG_DATA */
brw_upload_abo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
- &brw->cs.base, &brw->cs.prog_data->base);
+ &brw->cs.base, brw->cs.base.prog_data);
}
}
if (prog) {
/* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
- &brw->cs.base, &brw->cs.prog_data->base);
+ &brw->cs.base, brw->cs.base.prog_data);
}
}
static uint32_t
get_image_format(struct brw_context *brw, mesa_format format, GLenum access)
{
- const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
uint32_t hw_format = brw_format_for_mesa_format(format);
if (access == GL_WRITE_ONLY) {
return hw_format;
mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED ?
INTEL_AUX_BUFFER_DISABLED : 0;
brw_emit_surface_state(brw, mt, flags, mt->target, view,
- surface_state_infos[brw->gen].tex_mocs,
+ tex_mocs[brw->gen],
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER,
access == GL_READ_ONLY ? 0 :
if (prog) {
/* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
- &brw->wm.base, &brw->wm.prog_data->base);
+ &brw->wm.base, brw->wm.base.prog_data);
}
}
/* _NEW_PROGRAM */
struct gl_shader_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+ /* BRW_NEW_CS_PROG_DATA */
+ const struct brw_cs_prog_data *cs_prog_data =
+ brw_cs_prog_data(brw->cs.base.prog_data);
- if (prog && brw->cs.prog_data->uses_num_work_groups) {
+ if (prog && cs_prog_data->uses_num_work_groups) {
const unsigned surf_idx =
- brw->cs.prog_data->binding_table.work_groups_start;
+ cs_prog_data->binding_table.work_groups_start;
uint32_t *surf_offset = &brw->cs.base.surf_offset[surf_idx];
drm_intel_bo *bo;
uint32_t bo_offset;
const struct brw_tracked_state brw_cs_work_groups_surface = {
.dirty = {
.brw = BRW_NEW_BLORP |
+ BRW_NEW_CS_PROG_DATA |
BRW_NEW_CS_WORK_GROUPS
},
.emit = brw_upload_cs_work_groups_surface,
projects / mesa.git / blobdiff