INTEL_AUX_BUFFER_DISABLED = 1 << 1,
};
-struct surface_state_info {
- unsigned num_dwords;
- unsigned ss_align; /* Required alignment of RENDER_SURFACE_STATE in bytes */
- unsigned reloc_dw;
- unsigned aux_reloc_dw;
- unsigned tex_mocs;
- unsigned rb_mocs;
+uint32_t tex_mocs[] = {
+ [7] = GEN7_MOCS_L3,
+ [8] = BDW_MOCS_WB,
+ [9] = SKL_MOCS_WB,
};
-static const struct surface_state_info surface_state_infos[] = {
- [4] = {6, 32, 1, 0},
- [5] = {6, 32, 1, 0},
- [6] = {6, 32, 1, 0},
- [7] = {8, 32, 1, 6, GEN7_MOCS_L3, GEN7_MOCS_L3},
- [8] = {13, 64, 8, 10, BDW_MOCS_WB, BDW_MOCS_PTE},
- [9] = {16, 64, 8, 10, SKL_MOCS_WB, SKL_MOCS_PTE},
+uint32_t rb_mocs[] = {
+ [7] = GEN7_MOCS_L3,
+ [8] = BDW_MOCS_PTE,
+ [9] = SKL_MOCS_PTE,
};
static void
uint32_t mocs, uint32_t *surf_offset, int surf_index,
unsigned read_domains, unsigned write_domains)
{
- const struct surface_state_info ss_info = surface_state_infos[brw->gen];
uint32_t tile_x = mt->level[0].slice[0].x_offset;
uint32_t tile_y = mt->level[0].slice[0].y_offset;
uint32_t offset = mt->offset;
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
+ drm_intel_bo *aux_bo;
struct isl_surf *aux_surf = NULL, aux_surf_s;
uint64_t aux_offset = 0;
enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
- if (mt->mcs_mt && !(flags & INTEL_AUX_BUFFER_DISABLED)) {
+ if ((mt->mcs_buf || intel_miptree_sample_with_hiz(brw, mt)) &&
+ !(flags & INTEL_AUX_BUFFER_DISABLED)) {
intel_miptree_get_aux_isl_surf(brw, mt, &aux_surf_s, &aux_usage);
aux_surf = &aux_surf_s;
- assert(mt->mcs_mt->offset == 0);
- aux_offset = mt->mcs_mt->bo->offset64;
+
+ if (mt->mcs_buf) {
+ assert(mt->mcs_buf->offset == 0);
+ aux_bo = mt->mcs_buf->bo;
+ aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset;
+ } else {
+ aux_bo = mt->hiz_buf->aux_base.bo;
+ aux_offset = mt->hiz_buf->aux_base.bo->offset64 +
+ mt->hiz_buf->mt->offset;
+ }
/* We only really need a clear color if we also have an auxiliary
- * surfacae. Without one, it does nothing.
+ * surface. Without one, it does nothing.
*/
clear_color = intel_miptree_get_isl_clear_color(brw, mt);
}
- uint32_t *dw = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- ss_info.num_dwords * 4, ss_info.ss_align,
- surf_index, surf_offset);
+ void *state = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ brw->isl_dev.ss.size,
+ brw->isl_dev.ss.align,
+ surf_index, surf_offset);
- isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = &view,
+ isl_surf_fill_state(&brw->isl_dev, state, .surf = &surf, .view = &view,
.address = mt->bo->offset64 + offset,
.aux_surf = aux_surf, .aux_usage = aux_usage,
.aux_address = aux_offset,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4 * ss_info.reloc_dw,
+ *surf_offset + brw->isl_dev.ss.addr_offset,
mt->bo, offset,
read_domains, write_domains);
* an ordinary reloc to do the necessary address translation.
*/
assert((aux_offset & 0xfff) == 0);
+ uint32_t *aux_addr = state + brw->isl_dev.ss.aux_addr_offset;
drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4 * ss_info.aux_reloc_dw,
- mt->mcs_mt->bo, dw[ss_info.aux_reloc_dw] & 0xfff,
+ *surf_offset + brw->isl_dev.ss.aux_addr_offset,
+ aux_bo, *aux_addr & 0xfff,
read_domains, write_domains);
}
}
uint32_t offset;
brw_emit_surface_state(brw, mt, flags, mt->target, view,
- surface_state_infos[brw->gen].rb_mocs,
+ rb_mocs[brw->gen],
&offset, surf_index,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
const struct intel_mipmap_tree *mt)
{
/* Nothing to disable. */
- if (!mt->mcs_mt)
+ if (!mt->mcs_buf)
return false;
/* There are special cases only for lossless compression. */
const int flags =
brw_disable_aux_surface(brw, mt) ? INTEL_AUX_BUFFER_DISABLED : 0;
brw_emit_surface_state(brw, mt, flags, mt->target, view,
- surface_state_infos[brw->gen].tex_mocs,
+ tex_mocs[brw->gen],
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, 0);
}
unsigned pitch,
bool rw)
{
- const struct surface_state_info ss_info = surface_state_infos[brw->gen];
-
uint32_t *dw = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- ss_info.num_dwords * 4, ss_info.ss_align,
+ brw->isl_dev.ss.size,
+ brw->isl_dev.ss.align,
out_offset);
isl_buffer_fill_state(&brw->isl_dev, dw,
.size = buffer_size,
.format = surface_format,
.stride = pitch,
- .mocs = ss_info.tex_mocs);
+ .mocs = tex_mocs[brw->gen]);
if (bo) {
drm_intel_bo_emit_reloc(brw->batch.bo,
- *out_offset + 4 * ss_info.reloc_dw,
+ *out_offset + brw->isl_dev.ss.addr_offset,
bo, buffer_offset,
I915_GEM_DOMAIN_SAMPLER,
(rw ? I915_GEM_DOMAIN_SAMPLER : 0));
{
struct brw_stage_state *stage_state = &brw->wm.base;
/* BRW_NEW_FRAGMENT_PROGRAM */
- struct brw_fragment_program *fp =
- (struct brw_fragment_program *) brw->fragment_program;
+ struct brw_program *fp = (struct brw_program *) brw->fragment_program;
/* BRW_NEW_FS_PROG_DATA */
struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_FRAGMENT);
/* _NEW_PROGRAM_CONSTANTS */
- brw_upload_pull_constants(brw, BRW_NEW_SURFACES, &fp->program.Base,
+ brw_upload_pull_constants(brw, BRW_NEW_SURFACES, &fp->program,
stage_state, prog_data);
}
/* BRW_NEW_FRAGMENT_PROGRAM */
if (!ctx->Extensions.MESA_shader_framebuffer_fetch &&
- brw->fragment_program &&
- brw->fragment_program->Base.nir->info->outputs_read) {
+ brw->fragment_program && brw->fragment_program->info.outputs_read) {
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
const int flags = brw->draw_aux_buffer_disabled[i] ?
INTEL_AUX_BUFFER_DISABLED : 0;
brw_emit_surface_state(brw, irb->mt, flags, target, view,
- surface_state_infos[brw->gen].tex_mocs,
+ tex_mocs[brw->gen],
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, 0);
mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED ?
INTEL_AUX_BUFFER_DISABLED : 0;
brw_emit_surface_state(brw, mt, flags, mt->target, view,
- surface_state_infos[brw->gen].tex_mocs,
+ tex_mocs[brw->gen],
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER,
access == GL_READ_ONLY ? 0 :
projects / mesa.git / blobdiff