* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <drm_fourcc.h>
+#include "drm-uapi/drm_fourcc.h"
#include <errno.h>
#include <time.h>
#include <unistd.h>
#include "main/hash.h"
#include "main/fbobject.h"
#include "main/version.h"
+#include "main/glthread.h"
#include "swrast/s_renderbuffer.h"
#include "util/ralloc.h"
+#include "util/disk_cache.h"
#include "brw_defines.h"
#include "brw_state.h"
#include "compiler/nir/nir.h"
#include "utils.h"
#include "util/disk_cache.h"
-#include "util/xmlpool.h"
+#include "util/driconf.h"
+#include "util/u_memory.h"
+
+#include "common/gen_defines.h"
static const __DRIconfigOptionsExtension brw_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
* DRI_CONF_BO_REUSE_ALL
*/
DRI_CONF_OPT_BEGIN_V(bo_reuse, enum, 1, "0:1")
- DRI_CONF_DESC_BEGIN(en, "Buffer object reuse")
+ DRI_CONF_DESC_BEGIN("Buffer object reuse")
DRI_CONF_ENUM(0, "Disable buffer object reuse")
DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
DRI_CONF_DESC_END
DRI_CONF_OPT_END
DRI_CONF_MESA_NO_ERROR("false")
+ DRI_CONF_MESA_GLTHREAD("false")
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_PRECISE_TRIG("false")
DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1)
- DRI_CONF_DESC(en, "Clamp the value of GL_MAX_SAMPLES to the "
+ DRI_CONF_DESC("Clamp the value of GL_MAX_SAMPLES to the "
"given integer. If negative, then do not clamp.")
DRI_CONF_OPT_END
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
- DRI_CONF_NO_RAST("false")
DRI_CONF_ALWAYS_FLUSH_BATCH("false")
DRI_CONF_ALWAYS_FLUSH_CACHE("false")
DRI_CONF_DISABLE_THROTTLING("false")
DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
+ DRI_CONF_FORCE_COMPAT_PROFILE("false")
DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
+ DRI_CONF_FORCE_GL_VENDOR()
DRI_CONF_OPT_BEGIN_B(shader_precompile, "true")
- DRI_CONF_DESC(en, "Perform code generation at shader link time.")
+ DRI_CONF_DESC("Perform code generation at shader link time.")
DRI_CONF_OPT_END
DRI_CONF_SECTION_END
DRI_CONF_SECTION_MISCELLANEOUS
DRI_CONF_GLSL_ZERO_INIT("false")
+ DRI_CONF_VS_POSITION_ALWAYS_INVARIANT("false")
DRI_CONF_ALLOW_RGB10_CONFIGS("false")
+ DRI_CONF_ALLOW_RGB565_CONFIGS("true")
+ DRI_CONF_ALLOW_FP16_CONFIGS("false")
DRI_CONF_SECTION_END
DRI_CONF_END
};
#include "brw_context.h"
-#include "i915_drm.h"
+#include "drm-uapi/i915_drm.h"
/**
* For debugging purposes, this returns a time in seconds.
.setTexBuffer = intelSetTexBuffer,
.setTexBuffer2 = intelSetTexBuffer2,
- .releaseTexBuffer = NULL,
+ .releaseTexBuffer = intelReleaseTexBuffer,
};
static void
struct gl_context *ctx = &brw->ctx;
+ _mesa_glthread_finish(ctx);
+
FLUSH_VERTICES(ctx, 0);
if (flags & __DRI2_FLUSH_DRAWABLE)
};
static const struct intel_image_format intel_image_formats[] = {
- { __DRI_IMAGE_FOURCC_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { DRM_FORMAT_ABGR16161616F, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR16161616F, 8 } } },
+
+ { DRM_FORMAT_XBGR16161616F, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR16161616F, 8 } } },
+
+ { DRM_FORMAT_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010, 4 } } },
- { __DRI_IMAGE_FOURCC_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { DRM_FORMAT_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010, 4 } } },
- { __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { DRM_FORMAT_ABGR2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010, 4 } } },
+
+ { DRM_FORMAT_XBGR2101010, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010, 4 } } },
+
+ { DRM_FORMAT_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
- { __DRI_IMAGE_FOURCC_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { DRM_FORMAT_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } },
{ __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } },
- { __DRI_IMAGE_FOURCC_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { __DRI_IMAGE_FOURCC_SXRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_SXRGB8, 4 } } },
+
+ { DRM_FORMAT_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } },
- { __DRI_IMAGE_FOURCC_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { DRM_FORMAT_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } },
- { __DRI_IMAGE_FOURCC_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { DRM_FORMAT_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555, 2 } } },
- { __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { DRM_FORMAT_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } },
- { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1,
+ { DRM_FORMAT_R8, __DRI_IMAGE_COMPONENTS_R, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
- { __DRI_IMAGE_FOURCC_R16, __DRI_IMAGE_COMPONENTS_R, 1,
+ { DRM_FORMAT_R16, __DRI_IMAGE_COMPONENTS_R, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 1 }, } },
- { __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1,
+ { DRM_FORMAT_GR88, __DRI_IMAGE_COMPONENTS_RG, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } },
- { __DRI_IMAGE_FOURCC_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1,
+ { DRM_FORMAT_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616, 2 }, } },
- { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { DRM_FORMAT_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
- { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { DRM_FORMAT_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
- { __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { DRM_FORMAT_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
+
+ { DRM_FORMAT_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
+
+ { DRM_FORMAT_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
+
+ { DRM_FORMAT_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } },
+ { DRM_FORMAT_AYUV, __DRI_IMAGE_COMPONENTS_AYUV, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } },
+
+ { DRM_FORMAT_XYUV8888, __DRI_IMAGE_COMPONENTS_XYUV, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 } } },
+
/* For YUYV and UYVY buffers, we set up two overlapping DRI images
* and treat them as planar buffers in the compositors.
* Plane 0 is GR88 and samples YU or YV pairs and places Y into
* V into A. This lets the texture sampler interpolate the Y
* components correctly when sampling from plane 0, and interpolate
* U and V correctly when sampling from plane 1. */
- { __DRI_IMAGE_FOURCC_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2,
+ { DRM_FORMAT_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
{ 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
- { __DRI_IMAGE_FOURCC_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2,
+ { DRM_FORMAT_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
{ 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }
};
}
mesa_format format = driImageFormatToGLFormat(dri_format);
+ /* Whether or not we support compression is based on the RGBA non-sRGB
+ * version of the format.
+ */
+ format = _mesa_format_fallback_rgbx_to_rgba(format);
format = _mesa_get_srgb_format_linear(format);
if (!isl_format_supports_ccs_e(devinfo,
brw_isl_format_for_mesa_format(format)))
return NULL;
}
-static boolean intel_lookup_fourcc(int dri_format, int *fourcc)
+static bool
+intel_image_get_fourcc(__DRIimage *image, int *fourcc)
{
+ if (image->planar_format) {
+ *fourcc = image->planar_format->fourcc;
+ return true;
+ }
+
for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
- if (intel_image_formats[i].planes[0].dri_format == dri_format) {
+ if (intel_image_formats[i].planes[0].dri_format == image->dri_format) {
*fourcc = intel_image_formats[i].fourcc;
return true;
}
level - mt->first_level);
image->height = minify(mt->surf.phys_level0_sa.height,
level - mt->first_level);
- image->pitch = mt->surf.row_pitch;
+ image->pitch = mt->surf.row_pitch_B;
image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
&image->tile_x,
brw_bo_reference(irb->mt->bo);
image->width = rb->Width;
image->height = rb->Height;
- image->pitch = irb->mt->surf.row_pitch;
+ image->pitch = irb->mt->surf.row_pitch_B;
image->dri_format = driGLFormatToImageFormat(image->format);
image->has_depthstencil = irb->mt->stencil_mt? true : false;
intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level, zoffset);
image->dri_format = driGLFormatToImageFormat(image->format);
image->has_depthstencil = iobj->mt->stencil_mt? true : false;
- if (image->dri_format == MESA_FORMAT_NONE) {
+ image->planar_format = iobj->planar_format;
+ if (image->dri_format == __DRI_IMAGE_FORMAT_NONE) {
*error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
free(image);
return NULL;
bool ok;
/* Callers of this may specify a modifier, or a dri usage, but not both. The
- * newer modifier interface deprecates the older usage flags newer modifier
- * interface deprecates the older usage flags.
+ * newer modifier interface deprecates the older usage flags.
*/
assert(!(use && count));
.samples = 1,
.usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
ISL_SURF_USAGE_TEXTURE_BIT |
- ISL_SURF_USAGE_STORAGE_BIT,
+ ISL_SURF_USAGE_STORAGE_BIT |
+ ((use & __DRI_IMAGE_USE_SCANOUT) ?
+ ISL_SURF_USAGE_DISPLAY_BIT : 0),
.tiling_flags = (1 << mod_info->tiling));
assert(ok);
if (!ok) {
return NULL;
}
- struct isl_surf aux_surf;
+ struct isl_surf aux_surf = {0,};
if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
- ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, 0);
+ ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, NULL, 0);
if (!ok) {
free(image);
return NULL;
}
} else {
assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
- aux_surf.size = 0;
+ aux_surf.size_B = 0;
}
/* We request that the bufmgr zero the buffer for us for two reasons:
* in the pass-through state which is what we want.
*/
image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
- surf.size + aux_surf.size,
+ surf.size_B + aux_surf.size_B,
+ BRW_MEMZONE_OTHER,
isl_tiling_to_i915_tiling(mod_info->tiling),
- surf.row_pitch, BO_ALLOC_ZEROED);
+ surf.row_pitch_B, BO_ALLOC_ZEROED);
if (image->bo == NULL) {
free(image);
return NULL;
}
image->width = width;
image->height = height;
- image->pitch = surf.row_pitch;
+ image->pitch = surf.row_pitch_B;
image->modifier = modifier;
- if (aux_surf.size) {
- image->aux_offset = surf.size;
- image->aux_pitch = aux_surf.row_pitch;
+ if (aux_surf.size_B) {
+ image->aux_offset = surf.size_B;
+ image->aux_pitch = aux_surf.row_pitch_B;
+ image->aux_size = aux_surf.size_B;
}
return image;
case __DRI_IMAGE_ATTRIB_STRIDE:
*value = image->pitch;
return true;
- case __DRI_IMAGE_ATTRIB_HANDLE:
- *value = brw_bo_export_gem_handle(image->bo);
+ case __DRI_IMAGE_ATTRIB_HANDLE: {
+ __DRIscreen *dri_screen = image->screen->driScrnPriv;
+ uint32_t handle;
+ if (brw_bo_export_gem_handle_for_device(image->bo,
+ dri_screen->fd,
+ &handle))
+ return false;
+ *value = handle;
return true;
+ }
case __DRI_IMAGE_ATTRIB_NAME:
return !brw_bo_flink(image->bo, (uint32_t *) value);
case __DRI_IMAGE_ATTRIB_FORMAT:
case __DRI_IMAGE_ATTRIB_FD:
return !brw_bo_gem_export_to_prime(image->bo, value);
case __DRI_IMAGE_ATTRIB_FOURCC:
- return intel_lookup_fourcc(image->dri_format, value);
+ return intel_image_get_fourcc(image, value);
case __DRI_IMAGE_ATTRIB_NUM_PLANES:
if (isl_drm_modifier_has_aux(image->modifier)) {
assert(!image->planar_format || image->planar_format->nplanes == 1);
return NULL;
brw_bo_reference(orig_image->bo);
+ image->screen = orig_image->screen;
image->bo = orig_image->bo;
image->internal_format = orig_image->internal_format;
image->planar_format = orig_image->planar_format;
image->tile_y = orig_image->tile_y;
image->has_depthstencil = orig_image->has_depthstencil;
image->data = loaderPrivate;
- image->dma_buf_imported = orig_image->dma_buf_imported;
image->aux_offset = orig_image->aux_offset;
image->aux_pitch = orig_image->aux_pitch;
image->strides[index] = strides[index];
mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format);
+ /* The images we will create are actually based on the RGBA non-sRGB
+ * version of the format.
+ */
+ format = _mesa_format_fallback_rgbx_to_rgba(format);
+ format = _mesa_get_srgb_format_linear(format);
ok = isl_surf_init(&screen->isl_dev, &surf,
.dim = ISL_SURF_DIM_2D,
.levels = 1,
.array_len = 1,
.samples = 1,
- .row_pitch = strides[index],
+ .row_pitch_B = strides[index],
.usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
ISL_SURF_USAGE_TEXTURE_BIT |
ISL_SURF_USAGE_STORAGE_BIT,
return NULL;
}
- const int end = offsets[index] + surf.size;
+ const int end = offsets[index] + surf.size_B;
if (size < end)
size = end;
}
return NULL;
}
- struct isl_surf aux_surf;
- ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf,
+ struct isl_surf aux_surf = {0,};
+ ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, NULL,
image->aux_pitch);
if (!ok) {
brw_bo_unreference(image->bo);
return NULL;
}
- const int end = image->aux_offset + aux_surf.size;
+ image->aux_size = aux_surf.size_B;
+
+ const int end = image->aux_offset + aux_surf.size_B;
if (size < end)
size = end;
} else {
return NULL;
}
- image->dma_buf_imported = true;
image->yuv_color_space = yuv_color_space;
image->sample_range = sample_range;
image->horizontal_siting = horizontal_siting;
image->vertical_siting = vertical_siting;
+ image->imported_dmabuf = true;
*error = __DRI_IMAGE_ERROR_SUCCESS;
return image;
loaderPrivate);
}
+static bool
+intel_image_format_is_supported(const struct gen_device_info *devinfo,
+ const struct intel_image_format *fmt)
+{
+ /* Currently, all formats with an intel_image_format are available on all
+ * platforms so there's really nothing to check there.
+ */
+
+#ifndef NDEBUG
+ if (fmt->nplanes == 1) {
+ mesa_format format = driImageFormatToGLFormat(fmt->planes[0].dri_format);
+ /* The images we will create are actually based on the RGBA non-sRGB
+ * version of the format.
+ */
+ format = _mesa_format_fallback_rgbx_to_rgba(format);
+ format = _mesa_get_srgb_format_linear(format);
+ enum isl_format isl_format = brw_isl_format_for_mesa_format(format);
+ assert(isl_format_supports_rendering(devinfo, isl_format));
+ }
+#endif
+
+ return true;
+}
+
static GLboolean
-intel_query_dma_buf_formats(__DRIscreen *screen, int max,
+intel_query_dma_buf_formats(__DRIscreen *_screen, int max,
int *formats, int *count)
{
- int i, j = 0;
+ struct intel_screen *screen = _screen->driverPrivate;
+ int num_formats = 0, i;
- if (max == 0) {
- *count = ARRAY_SIZE(intel_image_formats) - 1; /* not SARGB */
- return true;
- }
+ for (i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
+ /* These formats are valid DRI formats but do not exist in drm_fourcc.h
+ * in the Linux kernel. We don't want to accidentally advertise them
+ * them through the EGL layer.
+ */
+ if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888 ||
+ intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR8888 ||
+ intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SXRGB8888)
+ continue;
+
+ if (!intel_image_format_is_supported(&screen->devinfo,
+ &intel_image_formats[i]))
+ continue;
+
+ num_formats++;
+ if (max == 0)
+ continue;
- for (i = 0; i < (ARRAY_SIZE(intel_image_formats)) && j < max; i++) {
- if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888)
- continue;
- formats[j++] = intel_image_formats[i].fourcc;
+ formats[num_formats - 1] = intel_image_formats[i].fourcc;
+ if (num_formats >= max)
+ break;
}
- *count = j;
+ *count = num_formats;
return true;
}
if (f == NULL)
return false;
+ if (!intel_image_format_is_supported(&screen->devinfo, f))
+ return false;
+
for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) {
uint64_t modifier = supported_modifiers[i].modifier;
if (!modifier_is_supported(&screen->devinfo, f, 0, modifier))
for (i = 0; i < num_mods && i < max; i++) {
if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V ||
f->components == __DRI_IMAGE_COMPONENTS_Y_UV ||
- f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV) {
+ f->components == __DRI_IMAGE_COMPONENTS_AYUV ||
+ f->components == __DRI_IMAGE_COMPONENTS_XYUV ||
+ f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV ||
+ f->components == __DRI_IMAGE_COMPONENTS_Y_UXVX) {
external_only[i] = GL_TRUE;
}
else {
static __DRIimage *
intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
{
- int width, height, offset, stride, dri_format, index;
- const struct intel_image_format *f;
+ int width, height, offset, stride, size, dri_format;
__DRIimage *image;
- if (parent == NULL) {
+ if (parent == NULL)
return NULL;
- } else if (parent->planar_format == NULL) {
- const bool is_aux =
- isl_drm_modifier_has_aux(parent->modifier) && plane == 1;
- if (!is_aux)
- return NULL;
-
- width = parent->width;
- height = parent->height;
- dri_format = parent->dri_format;
- offset = parent->aux_offset;
- stride = parent->aux_pitch;
- } else {
- /* Planar formats don't support aux buffers/images */
- assert(!isl_drm_modifier_has_aux(parent->modifier));
- f = parent->planar_format;
- if (plane >= f->nplanes)
- return NULL;
+ width = parent->width;
+ height = parent->height;
- width = parent->width >> f->planes[plane].width_shift;
- height = parent->height >> f->planes[plane].height_shift;
+ const struct intel_image_format *f = parent->planar_format;
+
+ if (f && plane < f->nplanes) {
+ /* Use the planar format definition. */
+ width >>= f->planes[plane].width_shift;
+ height >>= f->planes[plane].height_shift;
dri_format = f->planes[plane].dri_format;
- index = f->planes[plane].buffer_index;
+ int index = f->planes[plane].buffer_index;
offset = parent->offsets[index];
stride = parent->strides[index];
+ size = height * stride;
+ } else if (plane == 0) {
+ /* The only plane of a non-planar image: copy the parent definition
+ * directly. */
+ dri_format = parent->dri_format;
+ offset = parent->offset;
+ stride = parent->pitch;
+ size = height * stride;
+ } else if (plane == 1 && parent->modifier != DRM_FORMAT_MOD_INVALID &&
+ isl_drm_modifier_has_aux(parent->modifier)) {
+ /* Auxiliary plane */
+ dri_format = parent->dri_format;
+ offset = parent->aux_offset;
+ stride = parent->aux_pitch;
+ size = parent->aux_size;
+ } else {
+ return NULL;
+ }
- if (offset + height * stride > parent->bo->size) {
- _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds");
- return NULL;
- }
+ if (offset + size > parent->bo->size) {
+ _mesa_warning(NULL, "intel_from_planar: subimage out of bounds");
+ return NULL;
}
image = intel_allocate_image(parent->screen, dri_format, loaderPrivate);
.queryDmaBufFormatModifierAttribs = intel_query_format_modifier_attribs,
};
-static uint64_t
-get_aperture_size(int fd)
-{
- struct drm_i915_gem_get_aperture aperture;
-
- if (drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture) != 0)
- return 0;
-
- return aperture.aper_size;
-}
-
static int
brw_query_renderer_integer(__DRIscreen *dri_screen,
int param, unsigned int *value)
case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY:
value[0] = 0;
if (brw_hw_context_set_priority(screen->bufmgr,
- 0, BRW_CONTEXT_HIGH_PRIORITY) == 0)
+ 0, GEN_CONTEXT_HIGH_PRIORITY) == 0)
value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH;
if (brw_hw_context_set_priority(screen->bufmgr,
- 0, BRW_CONTEXT_LOW_PRIORITY) == 0)
+ 0, GEN_CONTEXT_LOW_PRIORITY) == 0)
value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW;
/* reset to default last, just in case */
if (brw_hw_context_set_priority(screen->bufmgr,
- 0, BRW_CONTEXT_MEDIUM_PRIORITY) == 0)
+ 0, GEN_CONTEXT_MEDIUM_PRIORITY) == 0)
value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM;
return 0;
case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB:
return -1;
}
+static void
+brw_set_cache_funcs(__DRIscreen *dri_screen,
+ __DRIblobCacheSet set, __DRIblobCacheGet get)
+{
+ const struct intel_screen *const screen =
+ (struct intel_screen *) dri_screen->driverPrivate;
+
+ if (!screen->disk_cache)
+ return;
+
+ disk_cache_set_callbacks(screen->disk_cache, set, get);
+}
+
static const __DRI2rendererQueryExtension intelRendererQueryExtension = {
.base = { __DRI2_RENDERER_QUERY, 1 },
.base = { __DRI2_ROBUSTNESS, 1 }
};
+static const __DRI2blobExtension intelBlobExtension = {
+ .base = { __DRI2_BLOB, 1 },
+ .set_cache_funcs = brw_set_cache_funcs
+};
+
+static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension = {
+ .base = { __DRI_MUTABLE_RENDER_BUFFER_DRIVER, 1 },
+};
+
static const __DRIextension *screenExtensions[] = {
&intelTexBufferExtension.base,
&intelFenceExtension.base,
&intelFlushExtension.base,
&intelImageExtension.base,
&intelRendererQueryExtension.base,
+ &intelMutableRenderBufferExtension.base,
&dri2ConfigQueryExtension.base,
&dri2NoErrorExtension.base,
+ &intelBlobExtension.base,
NULL
};
&intelFlushExtension.base,
&intelImageExtension.base,
&intelRendererQueryExtension.base,
+ &intelMutableRenderBufferExtension.base,
&dri2ConfigQueryExtension.base,
&dri2Robustness.base,
&dri2NoErrorExtension.base,
+ &intelBlobExtension.base,
NULL
};
gp.param = param;
gp.value = value;
- if (drmIoctl(screen->driScrnPriv->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) {
+ if (drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) {
ret = -errno;
if (ret != -EINVAL)
_mesa_warning(NULL, "drm_i915_getparam: %d", ret);
{
struct intel_screen *screen = sPriv->driverPrivate;
- brw_bufmgr_destroy(screen->bufmgr);
+ brw_bufmgr_unref(screen->bufmgr);
driDestroyOptionInfo(&screen->optionCache);
disk_cache_destroy(screen->disk_cache);
fb->Visual.samples = num_samples;
}
- if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) {
+ if (mesaVis->redBits == 16 && mesaVis->alphaBits > 0 && mesaVis->floatMode) {
+ rgbFormat = MESA_FORMAT_RGBA_FLOAT16;
+ } else if (mesaVis->redBits == 16 && mesaVis->floatMode) {
+ rgbFormat = MESA_FORMAT_RGBX_FLOAT16;
+ } else if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) {
rgbFormat = mesaVis->redMask == 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
: MESA_FORMAT_R10G10B10A2_UNORM;
} else if (mesaVis->redBits == 10) {
} else if (mesaVis->redBits == 5) {
rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM
: MESA_FORMAT_B5G6R5_UNORM;
+ } else if (mesaVis->alphaBits == 0) {
+ rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_SRGB
+ : MESA_FORMAT_B8G8R8X8_SRGB;
+ fb->Visual.sRGBCapable = true;
} else if (mesaVis->sRGBCapable) {
rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
: MESA_FORMAT_B8G8R8A8_SRGB;
- } else if (mesaVis->alphaBits == 0) {
- rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
- : MESA_FORMAT_B8G8R8X8_UNORM;
+ fb->Visual.sRGBCapable = true;
} else {
rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
: MESA_FORMAT_B8G8R8A8_SRGB;
if (getenv("INTEL_NO_HW") != NULL)
screen->no_hw = true;
- screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd);
+ bool bo_reuse = false;
+ int bo_reuse_mode = driQueryOptioni(&screen->optionCache, "bo_reuse");
+ switch (bo_reuse_mode) {
+ case DRI_CONF_BO_REUSE_DISABLED:
+ break;
+ case DRI_CONF_BO_REUSE_ALL:
+ bo_reuse = true;
+ break;
+ }
+
+ screen->bufmgr = brw_bufmgr_get_for_fd(&screen->devinfo, dri_screen->fd, bo_reuse);
if (screen->bufmgr == NULL) {
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
return false;
}
+ screen->fd = brw_bufmgr_get_fd(screen->bufmgr);
if (!intel_get_boolean(screen, I915_PARAM_HAS_EXEC_NO_RELOC)) {
fprintf(stderr, "[%s: %u] Kernel 3.9 required.\n", __func__, __LINE__);
static bool
intel_detect_swizzling(struct intel_screen *screen)
{
- struct brw_bo *buffer;
- unsigned flags = 0;
- uint32_t aligned_pitch;
+ /* Broadwell PRM says:
+ *
+ * "Before Gen8, there was a historical configuration control field to
+ * swizzle address bit[6] for in X/Y tiling modes. This was set in three
+ * different places: TILECTL[1:0], ARB_MODE[5:4], and
+ * DISP_ARB_CTL[14:13].
+ *
+ * For Gen8 and subsequent generations, the swizzle fields are all
+ * reserved, and the CPU's memory controller performs all address
+ * swizzling modifications."
+ */
+ if (screen->devinfo.gen >= 8)
+ return false;
+
uint32_t tiling = I915_TILING_X;
uint32_t swizzle_mode = 0;
-
- buffer = brw_bo_alloc_tiled_2d(screen->bufmgr, "swizzle test",
- 64, 64, 4, tiling, &aligned_pitch, flags);
+ struct brw_bo *buffer =
+ brw_bo_alloc_tiled(screen->bufmgr, "swizzle test", 32768,
+ BRW_MEMZONE_OTHER, tiling, 512, 0);
if (buffer == NULL)
return false;
brw_bo_get_tiling(buffer, &tiling, &swizzle_mode);
brw_bo_unreference(buffer);
- if (swizzle_mode == I915_BIT_6_SWIZZLE_NONE)
- return false;
- else
- return true;
+ return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
}
static int
bool success = false;
/* Create a zero'ed temporary buffer for reading our results */
- results = brw_bo_alloc(screen->bufmgr, "registers", 4096, 0);
+ results = brw_bo_alloc(screen->bufmgr, "registers", 4096, BRW_MEMZONE_OTHER);
if (results == NULL)
goto err;
- bo = brw_bo_alloc(screen->bufmgr, "batchbuffer", 4096, 0);
+ bo = brw_bo_alloc(screen->bufmgr, "batchbuffer", 4096, BRW_MEMZONE_OTHER);
if (bo == NULL)
goto err_results;
/* Don't bother with error checking - if the execbuf fails, the
* value won't be written and we'll just report that there's no access.
*/
- __DRIscreen *dri_screen = screen->driScrnPriv;
- drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
+ drmIoctl(screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
/* Check whether the value got written. */
void *results_map = brw_bo_map(NULL, results, MAP_READ);
return 0;
}
+static bool
+intel_allowed_format(__DRIscreen *dri_screen, mesa_format format)
+{
+ struct intel_screen *screen = dri_screen->driverPrivate;
+
+ /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
+ bool allow_rgba_ordering = intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING);
+ if (!allow_rgba_ordering &&
+ (format == MESA_FORMAT_R8G8B8A8_UNORM ||
+ format == MESA_FORMAT_R8G8B8X8_UNORM ||
+ format == MESA_FORMAT_R8G8B8A8_SRGB))
+ return false;
+
+ /* Shall we expose 10 bpc formats? */
+ bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache,
+ "allow_rgb10_configs");
+ if (!allow_rgb10_configs &&
+ (format == MESA_FORMAT_B10G10R10A2_UNORM ||
+ format == MESA_FORMAT_B10G10R10X2_UNORM))
+ return false;
+
+ /* Shall we expose 565 formats? */
+ bool allow_rgb565_configs = driQueryOptionb(&screen->optionCache,
+ "allow_rgb565_configs");
+ if (!allow_rgb565_configs && format == MESA_FORMAT_B5G6R5_UNORM)
+ return false;
+
+ /* Shall we expose fp16 formats? */
+ bool allow_fp16_configs = driQueryOptionb(&screen->optionCache,
+ "allow_fp16_configs");
+ allow_fp16_configs &= intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_FP16);
+ if (!allow_fp16_configs &&
+ (format == MESA_FORMAT_RGBA_FLOAT16 ||
+ format == MESA_FORMAT_RGBX_FLOAT16))
+ return false;
+
+ return true;
+}
+
static __DRIconfig**
intel_screen_make_configs(__DRIscreen *dri_screen)
{
MESA_FORMAT_B8G8R8X8_UNORM,
MESA_FORMAT_B8G8R8A8_SRGB,
+ MESA_FORMAT_B8G8R8X8_SRGB,
/* For 10 bpc, 30 bit depth framebuffers. */
MESA_FORMAT_B10G10R10A2_UNORM,
MESA_FORMAT_B10G10R10X2_UNORM,
+ MESA_FORMAT_RGBA_FLOAT16,
+ MESA_FORMAT_RGBX_FLOAT16,
+
/* The 32-bit RGBA format must not precede the 32-bit BGRA format.
* Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
* server may disagree on which format the GLXFBConfig represents,
/* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
MESA_FORMAT_R8G8B8X8_UNORM,
+
+ MESA_FORMAT_R8G8B8A8_SRGB,
};
- /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
+ /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
static const GLenum back_buffer_modes[] = {
__DRI_ATTRIB_SWAP_UNDEFINED, __DRI_ATTRIB_SWAP_NONE
};
uint8_t depth_bits[4], stencil_bits[4];
__DRIconfig **configs = NULL;
- /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
- unsigned num_formats;
- if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING))
- num_formats = ARRAY_SIZE(formats);
- else
- num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */
-
- /* Shall we expose 10 bpc formats? */
- bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache,
- "allow_rgb10_configs");
+ unsigned num_formats = ARRAY_SIZE(formats);
- /* Generate singlesample configs without accumulation buffer. */
+ /* Generate singlesample configs, each without accumulation buffer
+ * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
+ */
for (unsigned i = 0; i < num_formats; i++) {
__DRIconfig **new_configs;
- int num_depth_stencil_bits = 2;
+ int num_depth_stencil_bits = 1;
- if (!allow_rgb10_configs &&
- (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
- formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ if (!intel_allowed_format(dri_screen, formats[i]))
continue;
/* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
stencil_bits[0] = 0;
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
- depth_bits[1] = 16;
- stencil_bits[1] = 0;
+ if (devinfo->gen >= 8) {
+ depth_bits[num_depth_stencil_bits] = 16;
+ stencil_bits[num_depth_stencil_bits] = 0;
+ num_depth_stencil_bits++;
+ }
if (devinfo->gen >= 6) {
- depth_bits[2] = 24;
- stencil_bits[2] = 8;
- num_depth_stencil_bits = 3;
+ depth_bits[num_depth_stencil_bits] = 24;
+ stencil_bits[num_depth_stencil_bits] = 8;
+ num_depth_stencil_bits++;
}
} else {
- depth_bits[1] = 24;
- stencil_bits[1] = 8;
+ depth_bits[num_depth_stencil_bits] = 24;
+ stencil_bits[num_depth_stencil_bits] = 8;
+ num_depth_stencil_bits++;
}
new_configs = driCreateConfigs(formats[i],
num_depth_stencil_bits,
back_buffer_modes, 2,
singlesample_samples, 1,
- false, false);
+ false, false,
+ /*mutable_render_buffer*/ true);
configs = driConcatConfigs(configs, new_configs);
}
for (unsigned i = 0; i < num_formats; i++) {
__DRIconfig **new_configs;
- if (!allow_rgb10_configs &&
- (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
- formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ if (!intel_allowed_format(dri_screen, formats[i]))
continue;
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
- depth_bits[0] = 16;
- stencil_bits[0] = 0;
+ if (devinfo->gen >= 8) {
+ depth_bits[0] = 16;
+ stencil_bits[0] = 0;
+ } else if (devinfo->gen >= 6) {
+ depth_bits[0] = 24;
+ stencil_bits[0] = 8;
+ } else {
+ depth_bits[0] = 0;
+ stencil_bits[0] = 0;
+ }
} else {
depth_bits[0] = 24;
stencil_bits[0] = 8;
depth_bits, stencil_bits, 1,
back_buffer_modes, 1,
singlesample_samples, 1,
- true, false);
+ true, false, false);
configs = driConcatConfigs(configs, new_configs);
}
if (devinfo->gen < 6)
break;
- if (!allow_rgb10_configs &&
- (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
- formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ if (!intel_allowed_format(dri_screen, formats[i]))
continue;
__DRIconfig **new_configs;
depth_bits[0] = 0;
stencil_bits[0] = 0;
- if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
+ if (formats[i] == MESA_FORMAT_B5G6R5_UNORM && devinfo->gen >= 8) {
depth_bits[1] = 16;
stencil_bits[1] = 0;
} else {
back_buffer_modes, 1,
multisample_samples,
num_msaa_modes,
- false, false);
+ false, false, false);
configs = driConcatConfigs(configs, new_configs);
}
const bool has_astc = screen->devinfo.gen >= 9;
switch (screen->devinfo.gen) {
+ case 11:
case 10:
case 9:
case 8:
- dri_screen->max_gl_core_version = 45;
+ dri_screen->max_gl_core_version = 46;
dri_screen->max_gl_compat_version = 30;
dri_screen->max_gl_es1_version = 11;
dri_screen->max_gl_es2_version = has_astc ? 32 : 31;
}
}
-/**
- * Return the revision (generally the revid field of the PCI header) of the
- * graphics device.
- */
-int
-intel_device_get_revision(int fd)
-{
- struct drm_i915_getparam gp;
- int revision;
- int ret;
-
- memset(&gp, 0, sizeof(gp));
- gp.param = I915_PARAM_REVISION;
- gp.value = &revision;
-
- ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
- if (ret)
- revision = -1;
-
- return revision;
-}
-
static void
shader_debug_log_mesa(void *data, const char *fmt, ...)
{
va_start(args, fmt);
GLuint msg_id = 0;
- _mesa_gl_vdebug(&brw->ctx, &msg_id,
- MESA_DEBUG_SOURCE_SHADER_COMPILER,
- MESA_DEBUG_TYPE_OTHER,
- MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
+ _mesa_gl_vdebugf(&brw->ctx, &msg_id,
+ MESA_DEBUG_SOURCE_SHADER_COMPILER,
+ MESA_DEBUG_TYPE_OTHER,
+ MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
va_end(args);
}
if (brw->perf_debug) {
GLuint msg_id = 0;
- _mesa_gl_vdebug(&brw->ctx, &msg_id,
- MESA_DEBUG_SOURCE_SHADER_COMPILER,
- MESA_DEBUG_TYPE_PERFORMANCE,
- MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
+ _mesa_gl_vdebugf(&brw->ctx, &msg_id,
+ MESA_DEBUG_SOURCE_SHADER_COMPILER,
+ MESA_DEBUG_TYPE_PERFORMANCE,
+ MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
}
va_end(args);
}
-static int
-parse_devid_override(const char *devid_override)
-{
- static const struct {
- const char *name;
- int pci_id;
- } name_map[] = {
- { "brw", 0x2a02 },
- { "g4x", 0x2a42 },
- { "ilk", 0x0042 },
- { "snb", 0x0126 },
- { "ivb", 0x016a },
- { "hsw", 0x0d2e },
- { "byt", 0x0f33 },
- { "bdw", 0x162e },
- { "chv", 0x22B3 },
- { "skl", 0x1912 },
- { "bxt", 0x5A85 },
- { "kbl", 0x5912 },
- { "glk", 0x3185 },
- { "cnl", 0x5a52 },
- };
-
- for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
- if (!strcmp(name_map[i].name, devid_override))
- return name_map[i].pci_id;
- }
-
- return strtol(devid_override, NULL, 0);
-}
-
-/**
- * Get the PCI ID for the device. This can be overridden by setting the
- * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
- *
- * Returns -1 on ioctl failure.
- */
-static int
-get_pci_device_id(struct intel_screen *screen)
-{
- if (geteuid() == getuid()) {
- char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
- if (devid_override) {
- screen->no_hw = true;
- return parse_devid_override(devid_override);
- }
- }
-
- return intel_get_integer(screen, I915_PARAM_CHIPSET_ID);
-}
-
/**
* This is the driver specific part of the createNewScreen entry point.
* Called when using DRI2.
memset(&options, 0, sizeof(options));
driParseOptionInfo(&options, brw_config_options.xml);
- driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum, "i965");
+ driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum,
+ "i965", NULL, NULL, 0);
driDestroyOptionCache(&options);
screen->driScrnPriv = dri_screen;
dri_screen->driverPrivate = (void *) screen;
- screen->deviceID = get_pci_device_id(screen);
+ if (!gen_get_device_info_from_fd(dri_screen->fd, &screen->devinfo))
+ return NULL;
- if (!gen_get_device_info(screen->deviceID, &screen->devinfo))
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ screen->deviceID = devinfo->chipset_id;
+ screen->no_hw = devinfo->no_hw;
+
+ if (devinfo->gen >= 12) {
+ fprintf(stderr, "gen12 and newer are not supported on i965\n");
return NULL;
+ }
if (!intel_init_bufmgr(screen))
return NULL;
- const struct gen_device_info *devinfo = &screen->devinfo;
-
brw_process_intel_debug_variable();
if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {
screen->max_gtt_map_object_size = gtt_size / 4;
}
- screen->aperture_threshold = get_aperture_size(dri_screen->fd) * 3 / 4;
+ screen->aperture_threshold = devinfo->aperture_bytes * 3 / 4;
screen->hw_has_swizzling = intel_detect_swizzling(screen);
screen->hw_has_timestamp = intel_detect_timestamp(screen);
if (devinfo->gen >= 8 || screen->cmd_parser_version >= 5)
screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH;
+ if (intel_get_boolean(screen, I915_PARAM_HAS_CONTEXT_ISOLATION))
+ screen->kernel_features |= KERNEL_ALLOWS_CONTEXT_ISOLATION;
+
const char *force_msaa = getenv("INTEL_FORCE_MSAA");
if (force_msaa) {
screen->winsys_msaa_samples_override =
struct drm_i915_reset_stats stats;
memset(&stats, 0, sizeof(stats));
- const int ret = drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats);
+ const int ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats);
screen->has_context_reset_notification =
(ret != -1 || errno != EINVAL);
screen->compiler = brw_compiler_create(screen, devinfo);
screen->compiler->shader_debug_log = shader_debug_log_mesa;
screen->compiler->shader_perf_log = shader_perf_log_mesa;
- screen->compiler->constant_buffer_0_is_relative = true;
+
+ /* Changing the meaning of constant buffer pointers from a dynamic state
+ * offset to an absolute address is only safe if the kernel isolates other
+ * contexts from our changes.
+ */
+ screen->compiler->constant_buffer_0_is_relative = devinfo->gen < 8 ||
+ !(screen->kernel_features & KERNEL_ALLOWS_CONTEXT_ISOLATION);
+
+ screen->compiler->glsl_compiler_options[MESA_SHADER_VERTEX].PositionAlwaysInvariant = driQueryOptionb(&screen->optionCache, "vs_position_always_invariant");
+
screen->compiler->supports_pull_constants = true;
+ screen->compiler->compact_params = true;
+ screen->compiler->lower_variable_group_size = true;
screen->has_exec_fence =
intel_get_boolean(screen, I915_PARAM_HAS_EXEC_FENCE);
width,
height,
cpp,
+ BRW_MEMZONE_OTHER,
I915_TILING_X, &pitch,
BO_ALLOC_BUSY);
projects / mesa.git / blobdiff