Merge remote branch 'origin/master' into nv50-compiler

[mesa.git] / src / mesa / drivers / dri / r300 / compiler / radeon_opcodes.c

diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
index 1dc16855dc13a7e5bc7df35718e46a1da549342f..da495a3afaa7d9eb0b666456646e8454f562be9e 100644 (file)
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
@@ -94,6 +94,12 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .HasDstReg = 1,
                .IsComponentwise = 1
        },
+       {
+               .Opcode = RC_OPCODE_DP2,
+               .Name = "DP2",
+               .NumSrcRegs = 2,
+               .HasDstReg = 1
+       },
        {
                .Opcode = RC_OPCODE_DP3,
                .Name = "DP3",
@@ -294,6 +300,13 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .HasDstReg = 1,
                .IsComponentwise = 1
        },
+       {
+               .Opcode = RC_OPCODE_SSG,
+               .Name = "SSG",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1,
+               .IsComponentwise = 1
+       },
        {
                .Opcode = RC_OPCODE_SUB,
                .Name = "SUB",
@@ -385,6 +398,12 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .IsFlowControl = 1,
                .NumSrcRegs = 0,
        },
+       {
+               .Opcode = RC_OPCODE_CONT,
+               .Name = "CONT",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 0
+       },
        {
                .Opcode = RC_OPCODE_REPL_ALPHA,
                .Name = "REPL_ALPHA",
@@ -393,6 +412,10 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
        {
                .Opcode = RC_OPCODE_BEGIN_TEX,
                .Name = "BEGIN_TEX"
+       },
+       {
+               .Opcode = RC_OPCODE_KILP,
+               .Name = "KILP",
        }
 };
 
@@ -425,6 +448,10 @@ void rc_compute_sources_for_writemask(
                case RC_OPCODE_ARL:
                        srcmasks[0] |= RC_MASK_X;
                        break;
+               case RC_OPCODE_DP2:
+                       srcmasks[0] |= RC_MASK_XY;
+                       srcmasks[1] |= RC_MASK_XY;
+                       break;
                case RC_OPCODE_DP3:
                        srcmasks[0] |= RC_MASK_XYZ;
                        srcmasks[1] |= RC_MASK_XYZ;