Merge remote branch 'origin/master' into nv50-compiler

[mesa.git] / src / mesa / drivers / dri / r300 / compiler / radeon_opcodes.c

diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
index 9d289fce3429e439dce7cf5c4c59b77f2dfcf338..da495a3afaa7d9eb0b666456646e8454f562be9e 100644 (file)
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
@@ -26,6 +26,7 @@
  */
 
 #include "radeon_opcodes.h"
+#include "radeon_program.h"
 
 #include "radeon_program_constants.h"
 
@@ -58,6 +59,13 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .NumSrcRegs = 1,
                .HasDstReg = 1
        },
+       {
+               .Opcode = RC_OPCODE_CEIL,
+               .Name = "CEIL",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1,
+               .IsComponentwise = 1
+       },
        {
                .Opcode = RC_OPCODE_CMP,
                .Name = "CMP",
@@ -86,6 +94,12 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .HasDstReg = 1,
                .IsComponentwise = 1
        },
+       {
+               .Opcode = RC_OPCODE_DP2,
+               .Name = "DP2",
+               .NumSrcRegs = 2,
+               .HasDstReg = 1
+       },
        {
                .Opcode = RC_OPCODE_DP3,
                .Name = "DP3",
@@ -286,6 +300,13 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .HasDstReg = 1,
                .IsComponentwise = 1
        },
+       {
+               .Opcode = RC_OPCODE_SSG,
+               .Name = "SSG",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1,
+               .IsComponentwise = 1
+       },
        {
                .Opcode = RC_OPCODE_SUB,
                .Name = "SUB",
@@ -359,6 +380,30 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .IsFlowControl = 1,
                .NumSrcRegs = 0
        },
+       {
+               .Opcode = RC_OPCODE_BGNLOOP,
+               .Name = "BGNLOOP",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 0
+       },
+       {
+               .Opcode = RC_OPCODE_BRK,
+               .Name = "BRK",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 0
+       },
+       {
+               .Opcode = RC_OPCODE_ENDLOOP,
+               .Name = "ENDLOOP",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 0,
+       },
+       {
+               .Opcode = RC_OPCODE_CONT,
+               .Name = "CONT",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 0
+       },
        {
                .Opcode = RC_OPCODE_REPL_ALPHA,
                .Name = "REPL_ALPHA",
@@ -367,14 +412,19 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
        {
                .Opcode = RC_OPCODE_BEGIN_TEX,
                .Name = "BEGIN_TEX"
+       },
+       {
+               .Opcode = RC_OPCODE_KILP,
+               .Name = "KILP",
        }
 };
 
 void rc_compute_sources_for_writemask(
-               const struct rc_opcode_info * opcode,
+               const struct rc_instruction *inst,
                unsigned int writemask,
                unsigned int *srcmasks)
 {
+       const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
        srcmasks[0] = 0;
        srcmasks[1] = 0;
        srcmasks[2] = 0;
@@ -398,6 +448,10 @@ void rc_compute_sources_for_writemask(
                case RC_OPCODE_ARL:
                        srcmasks[0] |= RC_MASK_X;
                        break;
+               case RC_OPCODE_DP2:
+                       srcmasks[0] |= RC_MASK_XY;
+                       srcmasks[1] |= RC_MASK_XY;
+                       break;
                case RC_OPCODE_DP3:
                        srcmasks[0] |= RC_MASK_XYZ;
                        srcmasks[1] |= RC_MASK_XYZ;
@@ -406,21 +460,37 @@ void rc_compute_sources_for_writemask(
                        srcmasks[0] |= RC_MASK_XYZW;
                        srcmasks[1] |= RC_MASK_XYZW;
                        break;
-               case RC_OPCODE_TEX:
                case RC_OPCODE_TXB:
                case RC_OPCODE_TXP:
-                       srcmasks[0] |= RC_MASK_XYZW;
+                       srcmasks[0] |= RC_MASK_W;
+                       /* Fall through */
+               case RC_OPCODE_TEX:
+                       switch (inst->U.I.TexSrcTarget) {
+                               case RC_TEXTURE_1D:
+                                       srcmasks[0] |= RC_MASK_X;
+                                       break;
+                               case RC_TEXTURE_2D:
+                               case RC_TEXTURE_RECT:
+                               case RC_TEXTURE_1D_ARRAY:
+                                       srcmasks[0] |= RC_MASK_XY;
+                                       break;
+                               case RC_TEXTURE_3D:
+                               case RC_TEXTURE_CUBE:
+                               case RC_TEXTURE_2D_ARRAY:
+                                       srcmasks[0] |= RC_MASK_XYZ;
+                                       break;
+                       }
                        break;
                case RC_OPCODE_DST:
-                       srcmasks[0] |= 0x6;
-                       srcmasks[1] |= 0xa;
+                       srcmasks[0] |= RC_MASK_Y | RC_MASK_Z;
+                       srcmasks[1] |= RC_MASK_Y | RC_MASK_W;
                        break;
                case RC_OPCODE_EXP:
                case RC_OPCODE_LOG:
                        srcmasks[0] |= RC_MASK_XY;
                        break;
                case RC_OPCODE_LIT:
-                       srcmasks[0] |= 0xb;
+                       srcmasks[0] |= RC_MASK_X | RC_MASK_Y | RC_MASK_W;
                        break;
                default:
                        break;