* Authors:
* Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
#include <sched.h>
#include <errno.h>
#include "main/attrib.h"
-#include "main/enable.h"
-#include "main/blend.h"
#include "main/bufferobj.h"
-#include "main/buffers.h"
-#include "main/depth.h"
-#include "main/shaders.h"
-#include "main/texstate.h"
-#include "main/varray.h"
-#include "glapi/dispatch.h"
#include "swrast/swrast.h"
-#include "main/stencil.h"
-#include "main/matrix.h"
#include "main/glheader.h"
-#include "main/imports.h"
-#include "main/simple_list.h"
-#include "swrast/swrast.h"
+#include "util/simple_list.h"
#include "radeon_context.h"
#include "radeon_common.h"
-#include "radeon_state.h"
#include "radeon_ioctl.h"
-#include "radeon_tcl.h"
-#include "radeon_sanity.h"
-
-#define STANDALONE_MMIO
-#include "radeon_macros.h" /* for INREG() */
-
-#include "drirenderbuffer.h"
-#include "vblank.h"
#define RADEON_TIMEOUT 512
#define RADEON_IDLE_RETRY 16
*/
void radeonSetUpAtomList( r100ContextPtr rmesa )
{
- int i, mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
+ int i, mtu = rmesa->radeon.glCtx.Const.MaxTextureUnits;
make_empty_list(&rmesa->radeon.hw.atomlist);
rmesa->radeon.hw.atomlist.name = "atom-list";
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i]);
for (i = 0; i < 6; ++i)
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i]);
+ insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.stp);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.eye);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.grd);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.fog);
static void radeonEmitScissor(r100ContextPtr rmesa)
{
BATCH_LOCALS(&rmesa->radeon);
- if (!rmesa->radeon.radeonScreen->kernel_mm) {
- return;
- }
if (rmesa->radeon.state.scissor.enabled) {
BEGIN_BATCH(6);
OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
#if RADEON_OLD_PACKETS
BEGIN_BATCH(8);
OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 3);
- if (!rmesa->radeon.radeonScreen->kernel_mm) {
- OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
- } else {
- OUT_BATCH(rmesa->ioctl.vertex_offset);
- }
+ OUT_BATCH(rmesa->ioctl.vertex_offset);
OUT_BATCH(vertex_nr);
OUT_BATCH(vertex_format);
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
(vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT));
- if (rmesa->radeon.radeonScreen->kernel_mm) {
- radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->ioctl.bo,
- RADEON_GEM_DOMAIN_GTT,
- 0, 0);
- }
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
+ rmesa->ioctl.bo,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
END_BATCH();
#endif
}
-void radeonFlushElts( GLcontext *ctx )
+void radeonFlushElts( struct gl_context *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
BATCH_LOCALS(&rmesa->radeon);
int dwords = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw);
if (RADEON_DEBUG & RADEON_IOCTL)
- fprintf(stderr, "%s\n", __FUNCTION__);
+ fprintf(stderr, "%s\n", __func__);
assert( rmesa->radeon.dma.flush == radeonFlushElts );
rmesa->radeon.dma.flush = NULL;
nr = rmesa->tcl.elt_used;
#if RADEON_OLD_PACKETS
- if (rmesa->radeon.radeonScreen->kernel_mm) {
- dwords -= 2;
- }
+ dwords -= 2;
#endif
#if RADEON_OLD_PACKETS
rmesa->radeon.cmdbuf.cs->section_cdw += dwords;
#if RADEON_OLD_PACKETS
- if (rmesa->radeon.radeonScreen->kernel_mm) {
- radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->ioctl.bo,
- RADEON_GEM_DOMAIN_GTT,
- 0, 0);
- }
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
+ rmesa->ioctl.bo,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
#endif
END_BATCH();
if (RADEON_DEBUG & RADEON_SYNC) {
- fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
- radeonFinish( rmesa->radeon.glCtx );
+ fprintf(stderr, "%s: Syncing\n", __func__);
+ radeonFinish( &rmesa->radeon.glCtx );
}
}
BATCH_LOCALS(&rmesa->radeon);
if (RADEON_DEBUG & RADEON_IOCTL)
- fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
+ fprintf(stderr, "%s %d prim %x\n", __func__, min_nr, primitive);
assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
align_min_nr = (min_nr + 1) & ~1;
#if RADEON_OLD_PACKETS
- BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(align_min_nr)/4);
+ BEGIN_BATCH(2+ELTS_BUFSZ(align_min_nr)/4);
OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 0);
- if (!rmesa->radeon.radeonScreen->kernel_mm) {
- OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
- } else {
- OUT_BATCH(rmesa->ioctl.vertex_offset);
- }
+ OUT_BATCH(rmesa->ioctl.vertex_offset);
OUT_BATCH(rmesa->ioctl.vertex_max);
OUT_BATCH(vertex_format);
OUT_BATCH(primitive |
RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE);
#else
- BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr)/4);
+ BEGIN_BATCH(ELTS_BUFSZ(align_min_nr)/4);
OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0);
OUT_BATCH(vertex_format);
OUT_BATCH(primitive |
if (RADEON_DEBUG & RADEON_RENDER)
fprintf(stderr, "%s: header prim %x \n",
- __FUNCTION__, primitive);
+ __func__, primitive);
assert(!rmesa->radeon.dma.flush);
- rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
+ rmesa->radeon.glCtx.Driver.NeedFlush |= FLUSH_STORED_VERTICES;
rmesa->radeon.dma.flush = radeonFlushElts;
return retval;
#else
BATCH_LOCALS(&rmesa->radeon);
- if (RADEON_DEBUG & (RADEON_PRIMS|DEBUG_IOCTL))
+ if (RADEON_DEBUG & (RADEON_PRIMS|RADEON_IOCTL))
fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n",
- __FUNCTION__, vertex_size, offset);
+ __func__, vertex_size, offset);
BEGIN_BATCH(7);
OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, 2);
OUT_BATCH(1);
OUT_BATCH(vertex_size | (vertex_size << 8));
- OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
+ OUT_BATCH_RELOC(bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
#endif
int i;
if (RADEON_DEBUG & RADEON_IOCTL)
- fprintf(stderr, "%s\n", __FUNCTION__);
+ fprintf(stderr, "%s\n", __func__);
BEGIN_BATCH(sz+2+(nr * 2));
OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, sz - 1);
OUT_BATCH(nr);
- if (!rmesa->radeon.radeonScreen->kernel_mm) {
- for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
- (rmesa->radeon.tcl.aos[i].stride << 8) |
- (rmesa->radeon.tcl.aos[i + 1].components << 16) |
- (rmesa->radeon.tcl.aos[i + 1].stride << 24));
-
- voffset = rmesa->radeon.tcl.aos[i + 0].offset +
- offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
- OUT_BATCH_RELOC(voffset,
- rmesa->radeon.tcl.aos[i].bo,
- voffset,
- RADEON_GEM_DOMAIN_GTT,
- 0, 0);
- voffset = rmesa->radeon.tcl.aos[i + 1].offset +
- offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
- OUT_BATCH_RELOC(voffset,
- rmesa->radeon.tcl.aos[i+1].bo,
- voffset,
- RADEON_GEM_DOMAIN_GTT,
- 0, 0);
- }
-
- if (nr & 1) {
- OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
- (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
- voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
- OUT_BATCH_RELOC(voffset,
- rmesa->radeon.tcl.aos[nr - 1].bo,
- voffset,
- RADEON_GEM_DOMAIN_GTT,
- 0, 0);
- }
- } else {
+ {
for (i = 0; i + 1 < nr; i += 2) {
OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
(rmesa->radeon.tcl.aos[i].stride << 8) |
*/
#define RADEON_MAX_CLEARS 256
-static void radeonKernelClear(GLcontext *ctx, GLuint flags)
+static void radeonClear( struct gl_context *ctx, GLbitfield mask )
{
- r100ContextPtr rmesa = R100_CONTEXT(ctx);
- __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
- drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
- uint32_t clear;
- GLint ret, i;
- GLint cx, cy, cw, ch;
-
- LOCK_HARDWARE( &rmesa->radeon );
-
- /* compute region after locking: */
- cx = ctx->DrawBuffer->_Xmin;
- cy = ctx->DrawBuffer->_Ymin;
- cw = ctx->DrawBuffer->_Xmax - cx;
- ch = ctx->DrawBuffer->_Ymax - cy;
-
- /* Flip top to bottom */
- cx += dPriv->x;
- cy = dPriv->y + dPriv->h - cy - ch;
-
- /* Throttle the number of clear ioctls we do.
- */
- while ( 1 ) {
- int ret;
- drm_radeon_getparam_t gp;
-
- gp.param = RADEON_PARAM_LAST_CLEAR;
- gp.value = (int *)&clear;
- ret = drmCommandWriteRead( rmesa->radeon.dri.fd,
- DRM_RADEON_GETPARAM, &gp, sizeof(gp) );
-
- if ( ret ) {
- fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret );
- exit(1);
- }
-
- if ( sarea->last_clear - clear <= RADEON_MAX_CLEARS ) {
- break;
- }
-
- if ( rmesa->radeon.do_usleeps ) {
- UNLOCK_HARDWARE( &rmesa->radeon );
- DO_USLEEP( 1 );
- LOCK_HARDWARE( &rmesa->radeon );
- }
- }
-
- /* Send current state to the hardware */
- rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
-
- for ( i = 0 ; i < dPriv->numClipRects ; ) {
- GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects );
- drm_clip_rect_t *box = dPriv->pClipRects;
- drm_clip_rect_t *b = rmesa->radeon.sarea->boxes;
- drm_radeon_clear_t clear;
- drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
- GLint n = 0;
-
- if (cw != dPriv->w || ch != dPriv->h) {
- /* clear subregion */
- for ( ; i < nr ; i++ ) {
- GLint x = box[i].x1;
- GLint y = box[i].y1;
- GLint w = box[i].x2 - x;
- GLint h = box[i].y2 - y;
-
- if ( x < cx ) w -= cx - x, x = cx;
- if ( y < cy ) h -= cy - y, y = cy;
- if ( x + w > cx + cw ) w = cx + cw - x;
- if ( y + h > cy + ch ) h = cy + ch - y;
- if ( w <= 0 ) continue;
- if ( h <= 0 ) continue;
-
- b->x1 = x;
- b->y1 = y;
- b->x2 = x + w;
- b->y2 = y + h;
- b++;
- n++;
- }
- } else {
- /* clear whole buffer */
- for ( ; i < nr ; i++ ) {
- *b++ = box[i];
- n++;
- }
- }
-
- rmesa->radeon.sarea->nbox = n;
-
- clear.flags = flags;
- clear.clear_color = rmesa->radeon.state.color.clear;
- clear.clear_depth = rmesa->radeon.state.depth.clear;
- clear.color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- clear.depth_mask = rmesa->radeon.state.stencil.clear;
- clear.depth_boxes = depth_boxes;
-
- n--;
- b = rmesa->radeon.sarea->boxes;
- for ( ; n >= 0 ; n-- ) {
- depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1;
- depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
- depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2;
- depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2;
- depth_boxes[n].f[CLEAR_DEPTH] =
- (float)rmesa->radeon.state.depth.clear;
- }
-
- ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_CLEAR,
- &clear, sizeof(drm_radeon_clear_t));
+ r100ContextPtr rmesa = R100_CONTEXT(ctx);
+ GLuint hwmask, swmask;
+ GLuint hwbits = BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT |
+ BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL |
+ BUFFER_BIT_COLOR0;
- if ( ret ) {
- UNLOCK_HARDWARE( &rmesa->radeon );
- fprintf( stderr, "DRM_RADEON_CLEAR: return = %d\n", ret );
- exit( 1 );
- }
+ if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
+ rmesa->radeon.front_buffer_dirty = GL_TRUE;
}
- UNLOCK_HARDWARE( &rmesa->radeon );
-}
-
-static void radeonClear( GLcontext *ctx, GLbitfield mask )
-{
- r100ContextPtr rmesa = R100_CONTEXT(ctx);
- __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
- GLuint flags = 0;
- GLuint color_mask = 0;
- GLuint orig_mask = mask;
if ( RADEON_DEBUG & RADEON_IOCTL ) {
fprintf( stderr, "radeonClear\n");
}
- {
- LOCK_HARDWARE( &rmesa->radeon );
- UNLOCK_HARDWARE( &rmesa->radeon );
- if ( dPriv->numClipRects == 0 )
- return;
- }
-
radeon_firevertices(&rmesa->radeon);
- if ( mask & BUFFER_BIT_FRONT_LEFT ) {
- flags |= RADEON_FRONT;
- color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- mask &= ~BUFFER_BIT_FRONT_LEFT;
- }
-
- if ( mask & BUFFER_BIT_BACK_LEFT ) {
- flags |= RADEON_BACK;
- color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- mask &= ~BUFFER_BIT_BACK_LEFT;
- }
+ hwmask = mask & hwbits;
+ swmask = mask & ~hwbits;
- if ( mask & BUFFER_BIT_DEPTH ) {
- flags |= RADEON_DEPTH;
- mask &= ~BUFFER_BIT_DEPTH;
- }
-
- if ( (mask & BUFFER_BIT_STENCIL) ) {
- flags |= RADEON_STENCIL;
- mask &= ~BUFFER_BIT_STENCIL;
- }
-
- if ( mask ) {
+ if ( swmask ) {
if (RADEON_DEBUG & RADEON_FALLBACKS)
- fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
- _swrast_Clear( ctx, mask );
+ fprintf(stderr, "%s: swrast clear, mask: %x\n", __func__, swmask);
+ _swrast_Clear( ctx, swmask );
}
- if ( !flags )
+ if ( !hwmask )
return;
- if (rmesa->using_hyperz) {
- flags |= RADEON_USE_COMP_ZBUF;
-/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL)
- flags |= RADEON_USE_HIERZ; */
- if (((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
- ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
- flags |= RADEON_CLEAR_FASTZ;
- }
- }
-
- if (rmesa->radeon.radeonScreen->kernel_mm)
- radeonUserClear(ctx, orig_mask);
- else {
- radeonKernelClear(ctx, flags);
- rmesa->radeon.hw.all_dirty = GL_TRUE;
- }
+ radeonUserClear(ctx, hwmask);
}
-void radeonInitIoctlFuncs( GLcontext *ctx )
+void radeonInitIoctlFuncs( struct gl_context *ctx )
{
ctx->Driver.Clear = radeonClear;
ctx->Driver.Finish = radeonFinish;
projects / mesa.git / blobdiff