/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc., Austin, Texas.
+ VMware, Inc.
All Rights Reserved.
/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
#include "main/glheader.h"
-#include "main/imports.h"
#include "main/mtypes.h"
+#include "main/state.h"
#include "vbo/vbo.h"
#include "math/m_translate.h"
#include "tnl/tnl.h"
#include "tnl/t_pipeline.h"
-#include "math/m_translate.h"
#include "radeon_context.h"
#include "radeon_state.h"
#include "radeon_ioctl.h"
#include "radeon_tcl.h"
#include "radeon_swtcl.h"
#include "radeon_maos.h"
-
+#include "radeon_fog.h"
#define RADEON_TCL_MAX_SETUP 19
union emit_union { float f; GLuint ui; radeon_color_t rgba; };
static struct {
- void (*emit)( GLcontext *, GLuint, GLuint, void * );
+ void (*emit)( struct gl_context *, GLuint, GLuint, void * );
GLuint vertex_size;
GLuint vertex_format;
} setup_tab[RADEON_TCL_MAX_SETUP];
#define DO_RGBA (IND & RADEON_CP_VC_FRMT_PKCOLOR)
#define DO_SPEC_OR_FOG (IND & RADEON_CP_VC_FRMT_PKSPEC)
#define DO_SPEC ((IND & RADEON_CP_VC_FRMT_PKSPEC) && \
- (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR))
+ _mesa_need_secondary_color(ctx))
#define DO_FOG ((IND & RADEON_CP_VC_FRMT_PKSPEC) && ctx->Fog.Enabled && \
(ctx->Fog.FogCoordinateSource == GL_FOG_COORD))
-#define DO_TEX0 (IND & RADEON_CP_VC_FRMT_ST0)
-#define DO_TEX1 (IND & RADEON_CP_VC_FRMT_ST1)
-#define DO_TEX2 (IND & RADEON_CP_VC_FRMT_ST2)
-#define DO_PTEX (IND & RADEON_CP_VC_FRMT_Q0)
-#define DO_NORM (IND & RADEON_CP_VC_FRMT_N0)
+#define DO_TEX0 ((IND & RADEON_CP_VC_FRMT_ST0) != 0)
+#define DO_TEX1 ((IND & RADEON_CP_VC_FRMT_ST1) != 0)
+#define DO_TEX2 ((IND & RADEON_CP_VC_FRMT_ST2) != 0)
+#define DO_PTEX ((IND & RADEON_CP_VC_FRMT_Q0) != 0)
+#define DO_NORM ((IND & RADEON_CP_VC_FRMT_N0) != 0)
#define DO_TEX3 0
/***********************************************************************
- * Initialization
+ * Initialization
***********************************************************************/
}
-void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
+void radeonEmitArrays( struct gl_context *ctx, GLuint inputs )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb;
if (1) {
req |= RADEON_CP_VC_FRMT_Z;
- if (VB->ObjPtr->size == 4) {
+ if (VB->AttribPtr[_TNL_ATTRIB_POS]->size == 4) {
req |= RADEON_CP_VC_FRMT_W0;
}
}
req |= RADEON_ST_BIT(unit);
/* assume we need the 3rd coord if texgen is active for r/q OR at least
3 coords are submitted. This may not be 100% correct */
- if (VB->TexCoordPtr[unit]->size >= 3) {
+ if (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) {
req |= RADEON_Q_BIT(unit);
vtx |= RADEON_Q_BIT(unit);
}
- if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) )
+ if ( (ctx->Texture.FixedFuncUnit[unit].TexGenEnabled & (R_BIT | Q_BIT)) )
vtx |= RADEON_Q_BIT(unit);
- else if ((VB->TexCoordPtr[unit]->size >= 3) &&
- ((ctx->Texture.Unit[unit]._ReallyEnabled & (TEXTURE_CUBE_BIT)) == 0)) {
- GLuint swaptexmatcol = (VB->TexCoordPtr[unit]->size - 3);
+ else if ((VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) &&
+ (!ctx->Texture.Unit[unit]._Current ||
+ ctx->Texture.Unit[unit]._Current->Target != GL_TEXTURE_CUBE_MAP)) {
+ GLuint swaptexmatcol = (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size - 3);
if (((rmesa->NeedTexMatrix >> unit) & 1) &&
(swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1)))
radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ;
rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx;
}
- for (i = 0 ; i < RADEON_TCL_MAX_SETUP ; i++)
- if ((setup_tab[i].vertex_format & req) == req)
+ for (i = 0 ; i < RADEON_TCL_MAX_SETUP ; i++)
+ if ((setup_tab[i].vertex_format & req) == req)
break;
if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
radeonAllocDmaRegion( &rmesa->radeon,
&rmesa->radeon.tcl.aos[0].bo,
&rmesa->radeon.tcl.aos[0].offset,
- VB->Count * setup_tab[i].vertex_size * 4,
+ VB->Count * setup_tab[i].vertex_size * 4,
4);
/* The vertex code expects Obj to be clean to element 3. To fix
* this, add more vertex code (for obj-2, obj-3) or preferably move
- * to maos.
+ * to maos.
*/
- if (VB->ObjPtr->size < 3 ||
- (VB->ObjPtr->size == 3 &&
+ if (VB->AttribPtr[_TNL_ATTRIB_POS]->size < 3 ||
+ (VB->AttribPtr[_TNL_ATTRIB_POS]->size == 3 &&
(setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0))) {
_math_trans_4f( rmesa->tcl.ObjClean.data,
- VB->ObjPtr->data,
- VB->ObjPtr->stride,
+ VB->AttribPtr[_TNL_ATTRIB_POS]->data,
+ VB->AttribPtr[_TNL_ATTRIB_POS]->stride,
GL_FLOAT,
- VB->ObjPtr->size,
+ VB->AttribPtr[_TNL_ATTRIB_POS]->size,
0,
VB->Count );
- switch (VB->ObjPtr->size) {
+ switch (VB->AttribPtr[_TNL_ATTRIB_POS]->size) {
case 1:
_mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 1);
+ /* fallthrough */
case 2:
_mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 2);
+ /* fallthrough */
case 3:
if (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0) {
_mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 3);
}
+ /* fallthrough */
case 4:
default:
break;
}
- VB->ObjPtr = &rmesa->tcl.ObjClean;
+ VB->AttribPtr[_TNL_ATTRIB_POS] = &rmesa->tcl.ObjClean;
}
-
- setup_tab[i].emit( ctx, 0, VB->Count,
+ radeon_bo_map(rmesa->radeon.tcl.aos[0].bo, 1);
+ setup_tab[i].emit( ctx, 0, VB->Count,
rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset);
-
+ radeon_bo_unmap(rmesa->radeon.tcl.aos[0].bo);
// rmesa->radeon.tcl.aos[0].size = setup_tab[i].vertex_size;
rmesa->radeon.tcl.aos[0].stride = setup_tab[i].vertex_size;
rmesa->tcl.vertex_format = setup_tab[i].vertex_format;
projects / mesa.git / blobdiff