radeon: add missing fallthrough comments

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_maos_verts.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
index 985ad663c6db0a4a43c5af0037a9bc01c9eeb56b..fff6b8d2d059d8a1c6afefc6ffe4ac880888a493 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
+++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
@@ -1,7 +1,7 @@
 /**************************************************************************
 
 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
-                     Tungsten Graphics Inc., Austin, Texas.
+                     VMware, Inc.
 
 All Rights Reserved.
 
@@ -29,12 +29,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 /*
  * Authors:
- *   Keith Whitwell <keith@tungstengraphics.com>
+ *   Keith Whitwell <keithw@vmware.com>
  */
 
 #include "main/glheader.h"
-#include "main/imports.h"
 #include "main/mtypes.h"
+#include "main/state.h"
 
 #include "vbo/vbo.h"
 #include "math/m_translate.h"
@@ -63,14 +63,14 @@ static struct {
 #define DO_RGBA (IND & RADEON_CP_VC_FRMT_PKCOLOR)
 #define DO_SPEC_OR_FOG (IND & RADEON_CP_VC_FRMT_PKSPEC)
 #define DO_SPEC ((IND & RADEON_CP_VC_FRMT_PKSPEC) && \
-                (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR))
+                _mesa_need_secondary_color(ctx))
 #define DO_FOG  ((IND & RADEON_CP_VC_FRMT_PKSPEC) && ctx->Fog.Enabled && \
                 (ctx->Fog.FogCoordinateSource == GL_FOG_COORD))
-#define DO_TEX0 (IND & RADEON_CP_VC_FRMT_ST0)
-#define DO_TEX1 (IND & RADEON_CP_VC_FRMT_ST1)
-#define DO_TEX2 (IND & RADEON_CP_VC_FRMT_ST2)
-#define DO_PTEX (IND & RADEON_CP_VC_FRMT_Q0)
-#define DO_NORM (IND & RADEON_CP_VC_FRMT_N0)
+#define DO_TEX0 ((IND & RADEON_CP_VC_FRMT_ST0) != 0)
+#define DO_TEX1 ((IND & RADEON_CP_VC_FRMT_ST1) != 0)
+#define DO_TEX2 ((IND & RADEON_CP_VC_FRMT_ST2) != 0)
+#define DO_PTEX ((IND & RADEON_CP_VC_FRMT_Q0) != 0)
+#define DO_NORM ((IND & RADEON_CP_VC_FRMT_N0) != 0)
 
 #define DO_TEX3 0
 
@@ -279,7 +279,7 @@ static struct {
 
 
 /***********************************************************************
- *                         Initialization 
+ *                         Initialization
  ***********************************************************************/
 
 
@@ -351,10 +351,11 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs )
            req |= RADEON_Q_BIT(unit);
            vtx |= RADEON_Q_BIT(unit);
         }
-        if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) )
+        if ( (ctx->Texture.FixedFuncUnit[unit].TexGenEnabled & (R_BIT | Q_BIT)) )
            vtx |= RADEON_Q_BIT(unit);
         else if ((VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) &&
-                 ((ctx->Texture.Unit[unit]._ReallyEnabled & (TEXTURE_CUBE_BIT)) == 0)) {
+                 (!ctx->Texture.Unit[unit]._Current ||
+                   ctx->Texture.Unit[unit]._Current->Target != GL_TEXTURE_CUBE_MAP)) {
            GLuint swaptexmatcol = (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size - 3);
            if (((rmesa->NeedTexMatrix >> unit) & 1) &&
                 (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1)))
@@ -368,8 +369,8 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs )
       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx;
    }
 
-   for (i = 0 ; i < RADEON_TCL_MAX_SETUP ; i++) 
-      if ((setup_tab[i].vertex_format & req) == req) 
+   for (i = 0 ; i < RADEON_TCL_MAX_SETUP ; i++)
+      if ((setup_tab[i].vertex_format & req) == req)
         break;
 
    if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
@@ -382,12 +383,12 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs )
    radeonAllocDmaRegion( &rmesa->radeon,
                         &rmesa->radeon.tcl.aos[0].bo,
                         &rmesa->radeon.tcl.aos[0].offset,
-                        VB->Count * setup_tab[i].vertex_size * 4, 
+                        VB->Count * setup_tab[i].vertex_size * 4,
                         4);
 
    /* The vertex code expects Obj to be clean to element 3.  To fix
     * this, add more vertex code (for obj-2, obj-3) or preferably move
-    * to maos.  
+    * to maos.
     */
    if (VB->AttribPtr[_TNL_ATTRIB_POS]->size < 3 ||
        (VB->AttribPtr[_TNL_ATTRIB_POS]->size == 3 &&
@@ -404,12 +405,15 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs )
       switch (VB->AttribPtr[_TNL_ATTRIB_POS]->size) {
       case 1:
            _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 1);
+           /* fallthrough */
       case 2:
            _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 2);
+           /* fallthrough */
       case 3:
         if (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0) {
            _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 3);
         }
+        /* fallthrough */
       case 4:
       default:
         break;
@@ -420,7 +424,7 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs )
 
 
    radeon_bo_map(rmesa->radeon.tcl.aos[0].bo, 1);
-   setup_tab[i].emit( ctx, 0, VB->Count, 
+   setup_tab[i].emit( ctx, 0, VB->Count,
                      rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset);
    radeon_bo_unmap(rmesa->radeon.tcl.aos[0].bo);
    //   rmesa->radeon.tcl.aos[0].size = setup_tab[i].vertex_size;