Merge branch '7.8'
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_mipmap_tree.c
index 8c1f96ede0481663deeaba4399916cb1527983b9..7f5fb99fa4fa5a1cdfbfe701cb25b3647c4ba6f7 100644 (file)
@@ -96,26 +96,21 @@ unsigned get_texture_image_size(
        return rowStride * height * depth;
 }
 
-static unsigned is_pot(unsigned value)
-{
-       unsigned m;
-
-       for (m = 1; m < value; m *= 2) {}
-
-       return value == m;
-}
-
-unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width)
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling)
 {
        if (_mesa_is_format_compressed(format)) {
                return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
        } else {
                unsigned row_align;
 
-               if (is_pot(width)) {
-                       row_align = rmesa->texture_row_align - 1;
-               } else {
+               if (!_mesa_is_pow_two(width)) {
                        row_align = rmesa->texture_rect_row_align - 1;
+               } else if (tiling) {
+                       unsigned tileWidth, tileHeight;
+                       get_tile_size(format, &tileWidth, &tileHeight);
+                       row_align = tileWidth * _mesa_get_format_bytes(format) - 1;
+               } else {
+                       row_align = rmesa->texture_row_align - 1;
                }
 
                return (_mesa_format_row_stride(format, width) + row_align) & ~row_align;
@@ -137,7 +132,7 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
 
        height = _mesa_next_pow_two_32(lvl->height);
 
-       lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width);
+       lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits);
        lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, lvl->height, lvl->depth, mt->tilebits);
 
        assert(lvl->size > 0);
@@ -473,12 +468,9 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
 
                radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel];
 
-               /* TODO: bring back these assertions once the FBOs are fixed */
-#if 0
                assert(image->mtlevel == level);
                assert(srclvl->size == dstlvl->size);
                assert(srclvl->rowstride == dstlvl->rowstride);
-#endif
 
                radeon_bo_map(image->mt->bo, GL_FALSE);
 
@@ -561,6 +553,8 @@ static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj,
        }
 
        if (mtCount == 0) {
+               free(mtSizes);
+               free(mts);
                return NULL;
        }