Merge branch '7.8'

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_mipmap_tree.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 9ef3a84056a1d2e9568d4a93ab45802334cf5eaa..7f5fb99fa4fa5a1cdfbfe701cb25b3647c4ba6f7 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -36,6 +36,7 @@
 #include "main/texobj.h"
 #include "main/enums.h"
 #include "radeon_texture.h"
+#include "radeon_tile.h"
 
 static unsigned get_aligned_compressed_row_stride(
                gl_format format,
@@ -69,29 +70,51 @@ static unsigned get_aligned_compressed_row_stride(
        return stride;
 }
 
-static unsigned get_compressed_image_size(
+unsigned get_texture_image_size(
                gl_format format,
                unsigned rowStride,
-               unsigned height)
+               unsigned height,
+               unsigned depth,
+               unsigned tiling)
 {
-       unsigned blockWidth, blockHeight;
+       if (_mesa_is_format_compressed(format)) {
+               unsigned blockWidth, blockHeight;
 
-       _mesa_get_format_block_size(format, &blockWidth, &blockHeight);
+               _mesa_get_format_block_size(format, &blockWidth, &blockHeight);
+
+               return rowStride * ((height + blockHeight - 1) / blockHeight) * depth;
+       } else if (tiling) {
+               /* Need to align height to tile height */
+               unsigned tileWidth, tileHeight;
+
+               get_tile_size(format, &tileWidth, &tileHeight);
+               tileHeight--;
 
-       return rowStride * ((height + blockHeight - 1) / blockHeight);
+               height = (height + tileHeight) & ~tileHeight;
+       }
+
+       return rowStride * height * depth;
 }
 
-static int find_next_power_of_two(GLuint value)
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling)
 {
-       int i, tmp;
+       if (_mesa_is_format_compressed(format)) {
+               return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
+       } else {
+               unsigned row_align;
+
+               if (!_mesa_is_pow_two(width)) {
+                       row_align = rmesa->texture_rect_row_align - 1;
+               } else if (tiling) {
+                       unsigned tileWidth, tileHeight;
+                       get_tile_size(format, &tileWidth, &tileHeight);
+                       row_align = tileWidth * _mesa_get_format_bytes(format) - 1;
+               } else {
+                       row_align = rmesa->texture_row_align - 1;
+               }
 
-       i = 0;
-       tmp = value - 1;
-       while (tmp) {
-               tmp >>= 1;
-               i++;
+               return (_mesa_format_row_stride(format, width) + row_align) & ~row_align;
        }
-       return (1 << i);
 }
 
 /**
@@ -105,34 +128,15 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
        GLuint face, GLuint level, GLuint* curOffset)
 {
        radeon_mipmap_level *lvl = &mt->levels[level];
-       uint32_t row_align;
        GLuint height;
 
-       height = find_next_power_of_two(lvl->height);
-
-       /* Find image size in bytes */
-       if (_mesa_is_format_compressed(mt->mesaFormat)) {
-               lvl->rowstride = get_aligned_compressed_row_stride(mt->mesaFormat, lvl->width, rmesa->texture_compressed_row_align);
-               lvl->size = get_compressed_image_size(mt->mesaFormat, lvl->rowstride, height);
-       } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) {
-               row_align = rmesa->texture_rect_row_align - 1;
-               lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align;
-               lvl->size = lvl->rowstride * height;
-       } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) {
-               /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
-                * though the actual offset may be different (if texture is less than
-                * 32 bytes width) to the untiled case */
-               lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) * 2 + 31) & ~31;
-               lvl->size = lvl->rowstride * ((height + 1) / 2) * lvl->depth;
-       } else {
-               row_align = rmesa->texture_row_align - 1;
-               lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align;
-               lvl->size = lvl->rowstride * height * lvl->depth;
-       }
+       height = _mesa_next_pow_two_32(lvl->height);
+
+       lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits);
+       lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, lvl->height, lvl->depth, mt->tilebits);
+
        assert(lvl->size > 0);
 
-       /* All images are aligned to a 32-byte offset */
-       *curOffset = (*curOffset + 0x1f) & ~0x1f;
        lvl->faces[face].offset = *curOffset;
        *curOffset += lvl->size;
 
@@ -464,12 +468,9 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
 
                radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel];
 
-               /* TODO: bring back these assertions once the FBOs are fixed */
-#if 0
                assert(image->mtlevel == level);
                assert(srclvl->size == dstlvl->size);
                assert(srclvl->rowstride == dstlvl->rowstride);
-#endif
 
                radeon_bo_map(image->mt->bo, GL_FALSE);
 
@@ -552,6 +553,8 @@ static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj,
        }
 
        if (mtCount == 0) {
+               free(mtSizes);
+               free(mts);
                return NULL;
        }