/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
#include "main/glheader.h"
#include "main/enums.h"
#include "main/imports.h"
#include "main/macros.h"
-#include "main/simple_list.h"
+#include "util/simple_list.h"
#include "math/m_xform.h"
{ RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
};
-static void radeonSetVertexFormat( GLcontext *ctx )
+static void radeonSetVertexFormat( struct gl_context *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
- DECLARE_RENDERINPUTS(index_bitset);
+ GLbitfield64 index_bitset = tnl->render_inputs_bitset;
int fmt_0 = 0;
int offset = 0;
- RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
-
/* Important:
*/
if ( VB->NdcPtr != NULL ) {
* build up a hardware vertex.
*/
if ( !rmesa->swtcl.needproj ||
- RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { /* for projtex */
+ (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) {
+ /* for projtex */
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
offset = 4;
offset += 1;
rmesa->swtcl.specoffset = 0;
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
- RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset &
+ (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
#if MESA_LITTLE_ENDIAN
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
RADEON_CP_VC_FRMT_PKSPEC );
EMIT_PAD( 3 );
}
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
RADEON_CP_VC_FRMT_PKSPEC );
}
EMIT_PAD( 1 );
}
#else
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
RADEON_CP_VC_FRMT_PKSPEC );
}
EMIT_PAD( 1 );
}
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
RADEON_CP_VC_FRMT_PKSPEC );
#endif
}
- if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
+ if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
int i;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
switch (sz) {
radeon_cp_vc_frmts[i][0] );
break;
case 3:
+ if (ctx->Texture.Unit[i]._Current &&
+ ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
+ EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
+ radeon_cp_vc_frmts[i][1] );
+ } else {
+ EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
+ radeon_cp_vc_frmts[i][0] );
+ }
+ break;
case 4:
- if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
+ if (ctx->Texture.Unit[i]._Current &&
+ ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
radeon_cp_vc_frmts[i][1] );
} else {
}
}
- if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
- fmt_0 != rmesa->swtcl.vertex_format) {
+ if (rmesa->radeon.tnl_index_bitset != index_bitset ||
+ fmt_0 != rmesa->swtcl.vertex_format) {
RADEON_NEWPRIM(rmesa);
rmesa->swtcl.vertex_format = fmt_0;
rmesa->radeon.swtcl.vertex_size =
rmesa->radeon.swtcl.vertex_attr_count,
NULL, 0 );
rmesa->radeon.swtcl.vertex_size /= 4;
- RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
+ rmesa->radeon.tnl_index_bitset = index_bitset;
radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
"%s: vertex_size= %d floats\n", __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
}
}
}
-static void radeonRenderStart( GLcontext *ctx )
+static void radeonRenderStart( struct gl_context *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT( ctx );
* determine in advance whether or not the hardware can / should do the
* projection divide or Mesa should do it.
*/
-void radeonChooseVertexState( GLcontext *ctx )
+void radeonChooseVertexState( struct gl_context *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
+ GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
+ ctx->Polygon.BackMode != GL_FILL);
+ GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
* bigger one.
*/
- if ((!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ) &&
- !RENDERINPUTS_TEST( tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 ))
- || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
+ if ((0 == (tnl->render_inputs_bitset &
+ (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)
+ | BITFIELD64_BIT(_TNL_ATTRIB_COLOR1))))
+ || twosided
+ || unfilled) {
rmesa->swtcl.needproj = GL_TRUE;
se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
}
}
-void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
+void r100_swtcl_flush(struct gl_context *ctx, uint32_t current_offset)
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
/**********************************************************************/
-static GLboolean radeon_run_render( GLcontext *ctx,
+static GLboolean radeon_run_render( struct gl_context *ctx,
struct tnl_pipeline_stage *stage )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
return GL_TRUE;
radeon_prepare_render(&rmesa->radeon);
+ if (rmesa->radeon.NewGLState)
+ radeonValidateState( ctx );
tnl->Driver.Render.Start( ctx );
RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
};
-static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim );
-static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim );
-static void radeonResetLineStipple( GLcontext *ctx );
+static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim );
+static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim );
+static void radeonResetLineStipple( struct gl_context *ctx );
/***********************************************************************
#define DO_FALLBACK 0
#define DO_OFFSET 0
-#define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
-#define DO_TWOSIDE (IND & RADEON_TWOSIDE_BIT)
+#define DO_UNFILLED ((IND & RADEON_UNFILLED_BIT) != 0)
+#define DO_TWOSIDE ((IND & RADEON_TWOSIDE_BIT) != 0)
#define DO_FLAT 0
#define DO_TRI 1
#define DO_QUAD 1
/* Choose render functions */
/**********************************************************************/
-void radeonChooseRenderState( GLcontext *ctx )
+void radeonChooseRenderState( struct gl_context *ctx )
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
r100ContextPtr rmesa = R100_CONTEXT(ctx);
GLuint index = 0;
- GLuint flags = ctx->_TriangleCaps;
+ GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
+ ctx->Polygon.BackMode != GL_FILL);
+ GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
return;
- if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
- if (flags & DD_TRI_UNFILLED) index |= RADEON_UNFILLED_BIT;
+ if (twosided)
+ index |= RADEON_TWOSIDE_BIT;
+ if (unfilled)
+ index |= RADEON_UNFILLED_BIT;
if (index != rmesa->radeon.swtcl.RenderIndex) {
tnl->Driver.Render.Points = rast_tab[index].points;
/**********************************************************************/
-static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
+static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
}
}
-static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
+static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
+ GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
+ ctx->Polygon.BackMode != GL_FILL);
+
rmesa->radeon.swtcl.render_primitive = prim;
- if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
+ if (prim < GL_TRIANGLES || !unfilled)
radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
}
-static void radeonRenderFinish( GLcontext *ctx )
+static void radeonRenderFinish( struct gl_context *ctx )
{
}
-static void radeonResetLineStipple( GLcontext *ctx )
+static void radeonResetLineStipple( struct gl_context *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
RADEON_STATECHANGE( rmesa, lin );
}
-void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
+void radeonFallback( struct gl_context *ctx, GLuint bit, GLboolean mode )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
*/
_tnl_invalidate_vertex_state( ctx, ~0 );
_tnl_invalidate_vertices( ctx, ~0 );
- RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
+ rmesa->radeon.tnl_index_bitset = 0;
radeonChooseVertexState( ctx );
radeonChooseRenderState( ctx );
}
/* Initialization. */
/**********************************************************************/
-void radeonInitSwtcl( GLcontext *ctx )
+void radeonInitSwtcl( struct gl_context *ctx )
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
r100ContextPtr rmesa = R100_CONTEXT(ctx);
projects / mesa.git / blobdiff