#include "driver.h"
#include "drm.h"
+#include "memops.h"
#include "radeon.h"
#include "radeon_dri.h"
#include "radeon_reg.h"
#include "drm_sarea.h"
+static size_t radeon_drm_page_size;
-/* HACK - for now, put this here... */
-/* Alpha - this may need to be a variable to handle UP1x00 vs TITAN */
-#if defined(__alpha__)
-# define DRM_PAGE_SIZE 8192
-#elif defined(__ia64__)
-# define DRM_PAGE_SIZE getpagesize()
-#else
-# define DRM_PAGE_SIZE 4096
-#endif
+static int RadeonSetParam(const DRIDriverContext *ctx, int param, int value)
+{
+ drm_radeon_setparam_t sp;
+
+ memset(&sp, 0, sizeof(sp));
+ sp.param = param;
+ sp.value = value;
+
+ if (drmCommandWrite(ctx->drmFD, DRM_RADEON_SETPARAM, &sp, sizeof(sp))) {
+ return -1;
+ }
+ return 0;
+}
/**
* \brief Wait for free FIFO entries.
OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl);
+ if (info->colorTiling)
+ info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl);
-
/* Initialize and start the CP if required */
if ((err = drmCommandNone(ctx->drmFD, DRM_RADEON_CP_START)) != 0) {
fprintf(stderr, "%s: CP start %d\n", __FUNCTION__, err);
return 0;
}
- /* Workaround for some hardware bugs */
- if (info->ChipFamily < CHIP_FAMILY_R200)
- OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0020);
-
/* Modify the mode if the default mode is not appropriate for this
* particular combination of graphics card and AGP chipset.
*/
/* Disable fast write entirely - too many lockups.
*/
mode &= ~RADEON_AGP_MODE_MASK;
- switch (info->gartMode) {
+ switch (ctx->agpmode) {
case 4: mode |= RADEON_AGP_4X_MODE;
case 2: mode |= RADEON_AGP_2X_MODE;
case 1: default: mode |= RADEON_AGP_1X_MODE;
drmAgpRelease(ctx->drmFD);
return 0;
}
-
+ else
+ fprintf(stderr, "[gart] AGP enabled at %dx\n", ctx->agpmode);
+
+ /* Workaround for some hardware bugs */
+ if (info->ChipFamily < CHIP_FAMILY_R200)
+ OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000);
+
info->gartOffset = 0;
if ((ret = drmAgpAlloc(ctx->drmFD, info->gartSize*1024*1024, 0, NULL,
/* Initialize the CP ring buffer data */
info->ringStart = info->gartOffset;
- info->ringMapSize = info->ringSize*1024*1024 + DRM_PAGE_SIZE;
+ info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size;
info->ringReadOffset = info->ringStart + info->ringMapSize;
- info->ringReadMapSize = DRM_PAGE_SIZE;
+ info->ringReadMapSize = radeon_drm_page_size;
/* Reserve space for vertex/indirect buffers */
info->bufStart = info->ringReadOffset + info->ringReadMapSize;
fprintf(stderr, "[gart] Could not add ring mapping\n");
return 0;
}
- fprintf(stderr, "[gart] ring handle = 0x%08lx\n", info->ringHandle);
+ fprintf(stderr, "[gart] ring handle = 0x%08x\n", info->ringHandle);
if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
}
fprintf(stderr,
- "[gart] ring read ptr handle = 0x%08lx\n",
+ "[gart] ring read ptr handle = 0x%08lx\n",
info->ringReadPtrHandle);
if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
return 0;
}
fprintf(stderr,
- "[gart] vertex/indirect buffers handle = 0x%08lx\n",
+ "[gart] vertex/indirect buffers handle = 0x%08x\n",
info->bufHandle);
if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize,
return 0;
}
fprintf(stderr,
- "[gart] AGP texture map handle = 0x%08lx\n",
+ "[gart] AGP texture map handle = 0x%08lx\n",
info->gartTexHandle);
/* Initialize Radeon's AGP registers */
return 1;
}
+/* Initialize the PCI GART state. Request memory for use in PCI space,
+ * and initialize the Radeon registers to point to that memory.
+ */
+static int RADEONDRIPciInit(const DRIDriverContext *ctx, RADEONInfoPtr info)
+{
+ int ret;
+ int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
+ int s, l;
+
+ ret = drmScatterGatherAlloc(ctx->drmFD, info->gartSize*1024*1024,
+ &info->gartMemHandle);
+ if (ret < 0) {
+ fprintf(stderr, "[pci] Out of memory (%d)\n", ret);
+ return 0;
+ }
+ fprintf(stderr,
+ "[pci] %d kB allocated with handle 0x%08lx\n",
+ info->gartSize*1024, info->gartMemHandle);
+
+ info->gartOffset = 0;
+
+ /* Initialize the CP ring buffer data */
+ info->ringStart = info->gartOffset;
+ info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size;
+
+ info->ringReadOffset = info->ringStart + info->ringMapSize;
+ info->ringReadMapSize = radeon_drm_page_size;
+
+ /* Reserve space for vertex/indirect buffers */
+ info->bufStart = info->ringReadOffset + info->ringReadMapSize;
+ info->bufMapSize = info->bufSize*1024*1024;
+
+ /* Reserve the rest for AGP textures */
+ info->gartTexStart = info->bufStart + info->bufMapSize;
+ s = (info->gartSize*1024*1024 - info->gartTexStart);
+ l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
+ if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
+ info->gartTexMapSize = (s >> l) << l;
+ info->log2GARTTexGran = l;
+
+ if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
+ DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
+ fprintf(stderr,
+ "[pci] Could not add ring mapping\n");
+ return 0;
+ }
+ fprintf(stderr,
+ "[pci] ring handle = 0x%08x\n", info->ringHandle);
+
+ if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
+ DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
+ fprintf(stderr,
+ "[pci] Could not add ring read ptr mapping\n");
+ return 0;
+ }
+ fprintf(stderr,
+ "[pci] ring read ptr handle = 0x%08lx\n",
+ info->ringReadPtrHandle);
+
+ if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
+ DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
+ fprintf(stderr,
+ "[pci] Could not add vertex/indirect buffers mapping\n");
+ return 0;
+ }
+ fprintf(stderr,
+ "[pci] vertex/indirect buffers handle = 0x%08lx\n",
+ info->bufHandle);
+
+ if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize,
+ DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) {
+ fprintf(stderr,
+ "[pci] Could not add GART texture map mapping\n");
+ return 0;
+ }
+ fprintf(stderr,
+ "[pci] GART texture map handle = 0x%08x\n",
+ info->gartTexHandle);
+
+ return 1;
+}
+
/**
* \brief Initialize the kernel data structures and enable the CP engine.
/* This is the struct passed to the kernel module for its initialization */
drmInfo.sarea_priv_offset = sizeof(drm_sarea_t);
- drmInfo.is_pci = 0;
+ drmInfo.is_pci = ctx->isPCI;
drmInfo.cp_mode = RADEON_DEFAULT_CP_BM_MODE;
drmInfo.gart_size = info->gartSize*1024*1024;
drmInfo.ring_size = info->ringSize*1024*1024;
info->bufNumBufs = drmAddBufs(ctx->drmFD,
info->bufMapSize / RADEON_BUFFER_SIZE,
RADEON_BUFFER_SIZE,
- DRM_AGP_BUFFER,
+ ctx->isPCI ? DRM_SG_BUFFER : DRM_AGP_BUFFER,
info->bufStart);
if (info->bufNumBufs <= 0) {
{
int width_bytes = ctx->shared.virtualWidth * ctx->cpp;
int cpp = ctx->cpp;
- int bufferSize = ((ctx->shared.virtualHeight * width_bytes
- + RADEON_BUFFER_ALIGN)
- & ~RADEON_BUFFER_ALIGN);
+ int bufferSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
int depthSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes
- + RADEON_BUFFER_ALIGN)
- & ~RADEON_BUFFER_ALIGN);
+ + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
int l;
info->frontOffset = 0;
*/
info->textureSize = ctx->shared.fbSize - 2 * bufferSize - depthSize;
+ if (ctx->colorTiling==1)
+ {
+ info->textureSize = ctx->shared.fbSize - ((ctx->shared.fbSize - info->textureSize + width_bytes * 16 - 1) / (width_bytes * 16)) * (width_bytes*16);
+ }
+
if (info->textureSize < 0)
return 0;
}
/* Reserve space for textures */
- info->textureOffset = ((ctx->shared.fbSize - info->textureSize +
- RADEON_BUFFER_ALIGN) &
+ if (ctx->colorTiling==1)
+ {
+ info->textureOffset = ((ctx->shared.fbSize - info->textureSize) /
+ (width_bytes * 16)) * (width_bytes*16);
+ }
+ else
+ {
+ info->textureOffset = ((ctx->shared.fbSize - info->textureSize +
+ RADEON_BUFFER_ALIGN) &
~RADEON_BUFFER_ALIGN);
-
+ }
/* Reserve space for the shared depth
* buffer.
*/
(info->depthOffset >> 10));
return 1;
+}
+
+static int RADEONColorTilingInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
+{
+ int width_bytes = ctx->shared.virtualWidth * ctx->cpp;
+ int bufferSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes + RADEON_BUFFER_ALIGN)
+ & ~RADEON_BUFFER_ALIGN);
+ /* Setup color tiling */
+ if (info->drmMinor<14)
+ info->colorTiling=0;
+
+ if (info->colorTiling)
+ {
+
+ int colorTilingFlag;
+ drm_radeon_surface_alloc_t front,back;
+
+ RadeonSetParam(ctx, RADEON_SETPARAM_SWITCH_TILING, info->colorTiling ? 1 : 0);
+
+ /* Setup the surfaces */
+ if (info->ChipFamily < CHIP_FAMILY_R200)
+ colorTilingFlag=RADEON_SURF_TILE_COLOR_MACRO;
+ else
+ colorTilingFlag=R200_SURF_TILE_COLOR_MACRO;
+
+ front.address = info->frontOffset;
+ front.size = bufferSize;
+ front.flags = (width_bytes) | colorTilingFlag;
+ drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &front,sizeof(front));
+
+ back.address = info->backOffset;
+ back.size = bufferSize;
+ back.flags = (width_bytes) | colorTilingFlag;
+ drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &back,sizeof(back));
+
+ }
+ return 1;
}
"Radeon 9700 and newer cards\n");
return 0;
}
+
+ radeon_drm_page_size = getpagesize();
info->registerSize = ctx->MMIOSize;
- ctx->shared.SAREASize = DRM_PAGE_SIZE;
+ ctx->shared.SAREASize = SAREA_MAX;
/* Note that drmOpen will try to load the kernel module, if needed. */
ctx->drmFD = drmOpen("radeon", NULL );
/* Need to AddMap the framebuffer and mmio regions here:
*/
if (drmAddMap( ctx->drmFD,
- (drmHandle)ctx->FBStart,
+ (drm_handle_t)ctx->FBStart,
ctx->FBSize,
DRM_FRAME_BUFFER,
#ifndef _EMBEDDED
return 0;
}
- /* Initialize AGP */
- if (!RADEONDRIAgpInit(ctx, info)) {
- return 0;
+ if (ctx->isPCI) {
+ /* Initialize PCI */
+ if (!RADEONDRIPciInit(ctx, info))
+ return 0;
+ }
+ else {
+ /* Initialize AGP */
+ if (!RADEONDRIAgpInit(ctx, info))
+ return 0;
}
-
/* Memory manager setup */
if (!RADEONMemoryInit(ctx, info)) {
return 0;
}
+ RADEONColorTilingInit(ctx, info);
+
/* Initialize IRQ */
RADEONDRIIrqInit(ctx, info);
/* Initialize kernel gart memory manager */
RADEONDRIAgpHeapInit(ctx, info);
+ fprintf(stderr,"color tiling %sabled\n", info->colorTiling?"en":"dis");
+ fprintf(stderr,"page flipping %sabled\n", info->page_flip_enable?"en":"dis");
/* Initialize the SAREA private data structure */
{
drm_radeon_sarea_t *pSAREAPriv;
pSAREAPriv = (drm_radeon_sarea_t *)(((char*)ctx->pSAREA) +
sizeof(drm_sarea_t));
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
- pSAREAPriv->pfState = 1;
+ pSAREAPriv->pfState = info->page_flip_enable;
}
* the clear ioctl to do this, but would need to setup hw state
* first.
*/
- memset((char *)ctx->FBAddress + info->frontOffset,
+ drimemsetio((char *)ctx->FBAddress + info->frontOffset,
0,
info->frontPitch * ctx->cpp * ctx->shared.virtualHeight );
- memset((char *)ctx->FBAddress + info->backOffset,
+ drimemsetio((char *)ctx->FBAddress + info->backOffset,
0,
info->backPitch * ctx->cpp * ctx->shared.virtualHeight );
-
/* This is the struct passed to radeon_dri.so for its initialization */
ctx->driverClientMsg = malloc(sizeof(RADEONDRIRec));
ctx->driverClientMsgSize = sizeof(RADEONDRIRec);
pRADEONDRI->height = ctx->shared.virtualHeight;
pRADEONDRI->depth = ctx->bpp; /* XXX: depth */
pRADEONDRI->bpp = ctx->bpp;
- pRADEONDRI->IsPCI = 0;
- pRADEONDRI->AGPMode = info->gartMode;
+ pRADEONDRI->IsPCI = ctx->isPCI;
+ pRADEONDRI->AGPMode = ctx->agpmode;
pRADEONDRI->frontOffset = info->frontOffset;
pRADEONDRI->frontPitch = info->frontPitch;
pRADEONDRI->backOffset = info->backOffset;
}
-/**
- * \brief Establish the set of modes available for the display.
- *
- * \param ctx display handle.
- * \param numModes will receive the number of supported modes.
- * \param modes will point to the list of supported modes.
- *
- * \return one on success, or zero on failure.
- *
- * Allocates a single visual and fills it with information according to the
- * display bit depth. Supports only 16 and 32 bpp bit depths, aborting
- * otherwise.
- */
-const __GLcontextModes __glModes[] = {
-
- /* 32 bit, RGBA Depth=24 Stencil=8 */
- {.rgbMode = GL_TRUE, .colorIndexMode = GL_FALSE, .doubleBufferMode = GL_TRUE, .stereoMode = GL_FALSE,
- .haveAccumBuffer = GL_FALSE, .haveDepthBuffer = GL_TRUE, .haveStencilBuffer = GL_TRUE,
- .redBits = 8, .greenBits = 8, .blueBits = 8, .alphaBits = 8,
- .redMask = 0xff0000, .greenMask = 0xff00, .blueMask = 0xff, .alphaMask = 0xff000000,
- .rgbBits = 32, .indexBits = 0,
- .accumRedBits = 0, .accumGreenBits = 0, .accumBlueBits = 0, .accumAlphaBits = 0,
- .depthBits = 24, .stencilBits = 8,
- .numAuxBuffers= 0, .level = 0, .pixmapMode = GL_FALSE, },
-
- /* 16 bit, RGB Depth=16 */
- {.rgbMode = GL_TRUE, .colorIndexMode = GL_FALSE, .doubleBufferMode = GL_TRUE, .stereoMode = GL_FALSE,
- .haveAccumBuffer = GL_FALSE, .haveDepthBuffer = GL_TRUE, .haveStencilBuffer = GL_FALSE,
- .redBits = 5, .greenBits = 6, .blueBits = 5, .alphaBits = 0,
- .redMask = 0xf800, .greenMask = 0x07e0, .blueMask = 0x001f, .alphaMask = 0x0,
- .rgbBits = 16, .indexBits = 0,
- .accumRedBits = 0, .accumGreenBits = 0, .accumBlueBits = 0, .accumAlphaBits = 0,
- .depthBits = 16, .stencilBits = 0,
- .numAuxBuffers= 0, .level = 0, .pixmapMode = GL_FALSE, },
-};
-static int radeonInitContextModes( const DRIDriverContext *ctx,
- int *numModes, const __GLcontextModes **modes)
-{
- *numModes = sizeof(__glModes)/sizeof(__GLcontextModes *);
- *modes = &__glModes[0];
- return 1;
-}
-
-
/**
* \brief Validate the fbdev mode.
*
info->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL);
info->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
+ if (info->colorTiling)
+ info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
return 1;
}
unsigned char *RADEONMMIO = ctx->MMIOAddress;
RADEONInfoPtr info = ctx->driverPrivate;
+ RADEONColorTilingInit( ctx, info);
OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl);
+ if (info->colorTiling)
+ info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl);
-
+
return 1;
}
{
int dummy = ctx->shared.virtualWidth;
- switch (ctx->bpp / 8) {
- case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
- case 2: dummy = (ctx->shared.virtualWidth + 31) & ~31; break;
- case 3:
- case 4: dummy = (ctx->shared.virtualWidth + 15) & ~15; break;
+ if (ctx->colorTiling==1)
+ {
+ switch (ctx->bpp / 8) {
+ case 1: dummy = (ctx->shared.virtualWidth + 255) & ~255; break;
+ case 2: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
+ case 3:
+ case 4: dummy = (ctx->shared.virtualWidth + 63) & ~63; break;
+ }
+ } else {
+ switch (ctx->bpp / 8) {
+ case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
+ case 2: dummy = (ctx->shared.virtualWidth + 31) & ~31; break;
+ case 3:
+ case 4: dummy = (ctx->shared.virtualWidth + 15) & ~15; break;
+ }
}
ctx->shared.virtualWidth = dummy;
+ ctx->shared.Width = dummy;
}
+ fprintf(stderr,"shared virtual width is %d\n", ctx->shared.virtualWidth);
ctx->driverPrivate = (void *)info;
info->gartFastWrite = RADEON_DEFAULT_AGP_FAST_WRITE;
- info->gartMode = RADEON_DEFAULT_AGP_MODE;
info->gartSize = RADEON_DEFAULT_AGP_SIZE;
info->gartTexSize = RADEON_DEFAULT_AGP_TEX_SIZE;
info->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
info->ringSize = RADEON_DEFAULT_RING_SIZE;
+ info->page_flip_enable = RADEON_DEFAULT_PAGE_FLIP;
+ info->colorTiling = ctx->colorTiling;
info->Chipset = ctx->chipset;
* \sa DRIDriverRec.
*/
const struct DRIDriverRec __driDriver = {
- radeonInitContextModes,
radeonValidateMode,
radeonPostValidateMode,
radeonInitFBDev,
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