#include "main/imports.h"
#include "main/context.h"
-#include "main/macros.h"
#include "shader/program.h"
#include "shader/prog_instruction.h"
#include "shader/prog_parameter.h"
emitInfo->Subroutines = (struct gl_program **)
_mesa_realloc(emitInfo->Subroutines,
- n * sizeof(struct gl_program),
- (n + 1) * sizeof(struct gl_program));
+ n * sizeof(struct gl_program *),
+ (n + 1) * sizeof(struct gl_program *));
emitInfo->Subroutines[n] = ctx->Driver.NewProgram(ctx, emitInfo->prog->Target, 0);
emitInfo->Subroutines[n]->Parameters = emitInfo->prog->Parameters;
emitInfo->NumSubroutines++;
if (!n->Store) {
assert(defaultSize > 0);
n->Store = _slang_new_ir_storage(PROGRAM_TEMPORARY, -1, defaultSize);
+ if (!n->Store) {
+ return GL_FALSE;
+ }
}
/* now allocate actual register(s). I.e. set n->Store->Index >= 0 */
&srcRelAddr,
NULL,
NULL);
+ if (!inst) {
+ return NULL;
+ }
src[i] = &newSrc[i];
}
emit(emitInfo, n->Children[0]->Children[0]); /* A */
emit(emitInfo, n->Children[0]->Children[1]); /* B */
emit(emitInfo, n->Children[1]); /* C */
- alloc_node_storage(emitInfo, n, -1); /* dest */
+ if (!alloc_node_storage(emitInfo, n, -1)) { /* dest */
+ return NULL;
+ }
inst = emit_instruction(emitInfo,
OPCODE_MAD,
emit(emitInfo, n->Children[0]); /* A */
emit(emitInfo, n->Children[1]->Children[0]); /* B */
emit(emitInfo, n->Children[1]->Children[1]); /* C */
- alloc_node_storage(emitInfo, n, -1); /* dest */
+ if (!alloc_node_storage(emitInfo, n, -1)) { /* dest */
+ return NULL;
+ }
inst = emit_instruction(emitInfo,
OPCODE_MAD,
}
/* result storage */
- alloc_node_storage(emitInfo, n, -1);
+ if (!alloc_node_storage(emitInfo, n, -1)) {
+ return NULL;
+ }
inst = emit_instruction(emitInfo,
info->InstOpcode,
n->Children[0]->Store,
n->Children[1]->Store,
NULL);
+ if (!inst) {
+ return NULL;
+ }
inst_comment(inst, "Compare values");
/* Compute val = DOT(temp, temp) (reduction) */
&tempStore,
&tempStore,
NULL);
+ if (!inst) {
+ return NULL;
+ }
inst->SrcReg[0].Swizzle = inst->SrcReg[1].Swizzle = swizzle; /*override*/
inst_comment(inst, "Reduce vec to bool");
n->Store,
&zero,
NULL);
+ if (!inst) {
+ return NULL;
+ }
inst_comment(inst, "Invert true/false");
}
}
&srcStore0,
&srcStore1,
NULL);
+ if (!inst) {
+ return NULL;
+ }
inst_comment(inst, "Begin struct/array comparison");
}
else {
&srcStore0,
&srcStore1,
NULL);
+ if (!inst) {
+ return NULL;
+ }
/* ADD accTemp, accTemp, sneTemp; # like logical-OR */
inst = emit_instruction(emitInfo, OPCODE_ADD,
&accTemp, /* dest */
&accTemp,
&sneTemp,
NULL);
+ if (!inst) {
+ return NULL;
+ }
}
}
&accTemp,
&accTemp,
NULL);
+ if (!inst) {
+ return NULL;
+ }
inst_comment(inst, "End struct/array comparison");
if (n->Opcode == IR_EQUAL) {
n->Store,
&zero,
NULL);
+ if (!inst) {
+ return NULL;
+ }
inst_comment(inst, "Invert true/false");
}
* the intermediate result. Use a temp register instead.
*/
_mesa_bzero(&tmpNode, sizeof(tmpNode));
- alloc_node_storage(emitInfo, &tmpNode, n->Store->Size);
+ if (!alloc_node_storage(emitInfo, &tmpNode, n->Store->Size)) {
+ return NULL;
+ }
/* tmp = max(ch[0], ch[1]) */
inst = emit_instruction(emitInfo, OPCODE_MAX,
n->Children[0]->Store,
n->Children[1]->Store,
NULL);
+ if (!inst) {
+ return NULL;
+ }
/* n->dest = min(tmp, ch[2]) */
inst = emit_instruction(emitInfo, OPCODE_MIN,
n->Children[0]->Store,
NULL,
NULL);
- inst->SrcReg[0].Negate = NEGATE_XYZW;
+ if (inst) {
+ inst->SrcReg[0].Negate = NEGATE_XYZW;
+ }
return inst;
}
n->Children[1]->Store,
NULL,
NULL);
+ if (!inst) {
+ return NULL;
+ }
inst->TexShadow = shadow;
&srcStore,
NULL,
NULL);
+ if (!inst) {
+ return NULL;
+ }
inst_comment(inst, "IR_COPY block");
srcStore.Index++;
dstStore.Index++;
n->Children[1]->Store,
NULL,
NULL);
+ if (!inst) {
+ return NULL;
+ }
dstAnnot = storage_annotation(n->Children[0], emitInfo->prog);
srcAnnot = storage_annotation(n->Children[1], emitInfo->prog);
inst->Comment = instruction_annotation(inst->Opcode, dstAnnot,
n->Children[0]->Store,
NULL,
NULL);
+ if (!inst) {
+ return NULL;
+ }
inst->CondUpdate = GL_TRUE;
inst_comment(inst, "COND expr");
_slang_free_temp(emitInfo->vt, n->Store);
n->Children[0]->Store,
&zero,
NULL);
+ if (!inst) {
+ return NULL;
+ }
inst_comment(inst, "NOT");
free_node_storage(emitInfo->vt, n->Children[0]);
ifInst->DstReg.CondSwizzle = writemask_to_swizzle(condWritemask);
}
else {
+ struct prog_instruction *inst;
+
/* IF src[0] THEN ... */
- emit_instruction(emitInfo, OPCODE_IF,
- NULL, /* dst */
- n->Children[0]->Store, /* op0 */
- NULL,
- NULL);
+ inst = emit_instruction(emitInfo, OPCODE_IF,
+ NULL, /* dst */
+ n->Children[0]->Store, /* op0 */
+ NULL,
+ NULL);
+ if (!inst) {
+ return NULL;
+ }
}
}
else {
if (!inst) {
return NULL;
}
+ prog->Instructions[ifInstLoc].BranchTarget = prog->NumInstructions - 1;
}
else {
/* jump to endif instruction */
}
inst_comment(inst, "else");
inst->DstReg.CondMask = COND_TR; /* always branch */
+ prog->Instructions[ifInstLoc].BranchTarget = prog->NumInstructions;
}
- prog->Instructions[ifInstLoc].BranchTarget = prog->NumInstructions;
emit(emitInfo, n->Children[2]);
}
else {
}
}
- if (n->Children[2]) {
- prog->Instructions[elseInstLoc].BranchTarget = prog->NumInstructions;
+ if (elseInstLoc) {
+ /* point ELSE instruction BranchTarget at ENDIF */
+ if (emitInfo->EmitHighLevelInstructions) {
+ prog->Instructions[elseInstLoc].BranchTarget = prog->NumInstructions - 1;
+ }
+ else {
+ prog->Instructions[elseInstLoc].BranchTarget = prog->NumInstructions;
+ }
}
return NULL;
}
/* Done emitting loop code. Now walk over the loop's linked list of
* BREAK and CONT nodes, filling in their BranchTarget fields (which
- * will point to the ENDLOOP+1 or BGNLOOP instructions, respectively).
+ * will point to the corresponding ENDLOOP instruction.
*/
for (ir = n->List; ir; ir = ir->List) {
struct prog_instruction *inst = prog->Instructions + ir->InstLocation;
ir->Opcode == IR_BREAK_IF_TRUE) {
assert(inst->Opcode == OPCODE_BRK ||
inst->Opcode == OPCODE_BRA);
- /* go to instruction after end of loop */
- inst->BranchTarget = endInstLoc + 1;
+ /* go to instruction at end of loop */
+ if (emitInfo->EmitHighLevelInstructions) {
+ inst->BranchTarget = endInstLoc;
+ }
+ else {
+ inst->BranchTarget = endInstLoc + 1;
+ }
}
else {
assert(ir->Opcode == IR_CONT ||
n->Children[0]->Store,
NULL,
NULL);
+ if (!inst) {
+ return NULL;
+ }
n->InstLocation = emitInfo->prog->NumInstructions;
inst = new_instruction(emitInfo, opcode);
}
emitInfo->prog->Instructions[ifInstLoc].BranchTarget
- = emitInfo->prog->NumInstructions;
+ = emitInfo->prog->NumInstructions - 1;
return inst;
}
}
indexStore, /* the index */
&elemSizeStore,
NULL);
+ if (!inst) {
+ return NULL;
+ }
indexStore = indexTemp;
}
indexStore, /* the index */
&indirectArray, /* indirect array base */
NULL);
+ if (!inst) {
+ return NULL;
+ }
indexStore = indexTemp;
}